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Commit 1306b20d authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'omap-for-v3.19/gpmc-move-v2' of... 

Merge tag 'omap-for-v3.19/gpmc-move-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/omap-gpmc

Pull "move omap gpmc to drivers finally" from Tony Lindgren:

We can finally move the GPMC code to live in drivers/memory for
further clean up work.

Note that we still have dependencies to the legacy booting for
omap3 board-*.c files for setting up the board specific memory
timings. For that we need the timing related things still exposed
in include/linux/omap-gpmc.h. This will all become private data
to the GPMC driver once the legacy booting support can be dropped.

* tag 'omap-for-v3.19/gpmc-move-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  memory: gpmc: Move omap gpmc code to live under drivers
  ARM: OMAP2+: Move GPMC initcall to devices.c
  ARM: OMAP2+: Prepare to move GPMC to drivers by platform data header
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 594b5d51 18640193
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MAINTAINERS
View file @ 1306b20d
......@@ -6633,6 +6633,14 @@ L: linux-omap@vger.kernel.org
S: Maintained
F: sound/soc/omap/
OMAP GENERAL PURPOSE MEMORY CONTROLLER SUPPORT
M: Roger Quadros <rogerq@ti.com>
M: Tony Lindgren <tony@atomide.com>
L: linux-omap@vger.kernel.org
S: Maintained
F: drivers/memory/omap-gpmc.c
F: arch/arm/mach-omap2/*gpmc*
OMAP FRAMEBUFFER SUPPORT
M: Tomi Valkeinen <tomi.valkeinen@ti.com>
L: linux-fbdev@vger.kernel.org
......
arch/arm/mach-omap2/Kconfig
View file @ 1306b20d
......@@ -79,7 +79,9 @@ config ARCH_OMAP2PLUS
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select MACH_OMAP_GENERIC
select MEMORY
select OMAP_DM_TIMER
select OMAP_GPMC
select PINCTRL
select SOC_BUS
select TI_PRIV_EDMA
......
arch/arm/mach-omap2/Makefile
View file @ 1306b20d
......@@ -6,7 +6,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-omap/include
# Common support
obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o sram.o drm.o
......
arch/arm/mach-omap2/board-am3517crane.c
View file @ 1306b20d
......@@ -24,6 +24,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/omap-gpmc.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......
arch/arm/mach-omap2/board-cm-t35.c
View file @ 1306b20d
......@@ -25,6 +25,7 @@
#include <linux/input/matrix_keypad.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/at24.h>
......@@ -51,8 +52,6 @@
#include "sdram-micron-mt46h32m32lf-6.h"
#include "hsmmc.h"
#include "common-board-devices.h"
#include "gpmc.h"
#include "gpmc-nand.h"
#define CM_T35_GPIO_PENDOWN 57
#define SB_T35_USB_HUB_RESET_GPIO 167
......
arch/arm/mach-omap2/board-cm-t3517.c
View file @ 1306b20d
......@@ -28,6 +28,7 @@
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/omap-gpmc.h>
#include <linux/rtc-v3020.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
......@@ -41,7 +42,6 @@
#include "common.h"
#include <linux/platform_data/mtd-nand-omap2.h>
#include "gpmc.h"
#include "am35xx.h"
......@@ -50,7 +50,6 @@
#include "hsmmc.h"
#include "common-board-devices.h"
#include "am35xx-emac.h"
#include "gpmc-nand.h"
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cm_t3517_leds[] = {
......
arch/arm/mach-omap2/board-flash.c
View file @ 1306b20d
......@@ -13,6 +13,7 @@
*/
#include <linux/kernel.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
......@@ -23,8 +24,6 @@
#include "soc.h"
#include "common.h"
#include "board-flash.h"
#include "gpmc-onenand.h"
#include "gpmc-nand.h"
#define REG_FPGA_REV 0x10
#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
......
arch/arm/mach-omap2/board-flash.h
View file @ 1306b20d
......@@ -12,7 +12,6 @@
*/
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include "gpmc.h"
#define PDC_NOR 1
#define PDC_NAND 2
......
arch/arm/mach-omap2/board-n8x0.c
View file @ 1306b20d
......@@ -22,7 +22,6 @@
#include <linux/spi/spi.h>
#include <linux/usb/musb.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include <linux/mfd/menelaus.h>
#include <sound/tlv320aic3x.h>
......@@ -32,7 +31,6 @@
#include "common.h"
#include "mmc.h"
#include "soc.h"
#include "gpmc-onenand.h"
#include "common-board-devices.h"
#define TUSB6010_ASYNC_CS 1
......
arch/arm/mach-omap2/board-omap3pandora.c
View file @ 1306b20d
......@@ -24,6 +24,7 @@
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <linux/i2c/twl.h>
#include <linux/omap-gpmc.h>
#include <linux/wl12xx.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
......@@ -51,7 +52,6 @@
#include "sdram-micron-mt46h32m32lf-6.h"
#include "hsmmc.h"
#include "common-board-devices.h"
#include "gpmc-nand.h"
#define PANDORA_WIFI_IRQ_GPIO 21
#define PANDORA_WIFI_NRESET_GPIO 23
......
arch/arm/mach-omap2/board-rx51-peripherals.c
View file @ 1306b20d
......@@ -23,6 +23,7 @@
#include <linux/regulator/machine.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/omap-gpmc.h>
#include <linux/mmc/host.h>
#include <linux/power/isp1704_charger.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
......@@ -54,8 +55,6 @@
#include "omap-pm.h"
#include "hsmmc.h"
#include "common-board-devices.h"
#include "gpmc.h"
#include "gpmc-onenand.h"
#include "soc.h"
#include "omap-secure.h"
......
arch/arm/mach-omap2/devices.c
View file @ 1306b20d
......@@ -445,3 +445,29 @@ static int __init omap2_init_devices(void)
return 0;
}
omap_arch_initcall(omap2_init_devices);
static int __init omap_gpmc_init(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
char *oh_name = "gpmc";
/*
* if the board boots up with a populated DT, do not
* manually add the device from this initcall
*/
if (of_have_populated_dt())
return -ENODEV;
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return -ENODEV;
}
pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0);
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
return PTR_RET(pdev);
}
omap_postcore_initcall(omap_gpmc_init);
arch/arm/mach-omap2/gpmc-nand.c
View file @ 1306b20d
......@@ -12,14 +12,13 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/omap-gpmc.h>
#include <linux/mtd/nand.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include <asm/mach/flash.h>
#include "gpmc.h"
#include "soc.h"
#include "gpmc-nand.h"
/* minimum size for IO mapping */
#define NAND_IO_SIZE 4
......
arch/arm/mach-omap2/gpmc-nand.h deleted 100644 → 0
View file @ 594b5d51
/*
* arch/arm/mach-omap2/gpmc-nand.h
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __OMAP2_GPMC_NAND_H
#define __OMAP2_GPMC_NAND_H
#include "gpmc.h"
#include <linux/platform_data/mtd-nand-omap2.h>
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
extern int gpmc_nand_init(struct omap_nand_platform_data *d,
struct gpmc_timings *gpmc_t);
#else
static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
struct gpmc_timings *gpmc_t)
{
return 0;
}
#endif
#endif
arch/arm/mach-omap2/gpmc-onenand.c
View file @ 1306b20d
......@@ -15,14 +15,13 @@
#include <linux/platform_device.h>
#include <linux/mtd/onenand_regs.h>
#include <linux/io.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include <linux/err.h>
#include <asm/mach/flash.h>
#include "gpmc.h"
#include "soc.h"
#include "gpmc-onenand.h"
#define ONENAND_IO_SIZE SZ_128K
......
arch/arm/mach-omap2/gpmc-onenand.h deleted 100644 → 0
View file @ 594b5d51
/*
* arch/arm/mach-omap2/gpmc-onenand.h
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __OMAP2_GPMC_ONENAND_H
#define __OMAP2_GPMC_ONENAND_H
#include <linux/platform_data/mtd-onenand-omap2.h>
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
#else
#define board_onenand_data NULL
static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
{
}
#endif
#endif
arch/arm/mach-omap2/gpmc.h
View file @ 1306b20d
......@@ -6,226 +6,9 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Do not include this file in any new code, this will get removed
* once omap3 boots in device tree only mode.
*
*/
#ifndef __OMAP2_GPMC_H
#define __OMAP2_GPMC_H
#include <linux/platform_data/mtd-nand-omap2.h>
/* Maximum Number of Chip Selects */
#define GPMC_CS_NUM 8
#define GPMC_CS_CONFIG1 0x00
#define GPMC_CS_CONFIG2 0x04
#define GPMC_CS_CONFIG3 0x08
#define GPMC_CS_CONFIG4 0x0c
#define GPMC_CS_CONFIG5 0x10
#define GPMC_CS_CONFIG6 0x14
#define GPMC_CS_CONFIG7 0x18
#define GPMC_CS_NAND_COMMAND 0x1c
#define GPMC_CS_NAND_ADDRESS 0x20
#define GPMC_CS_NAND_DATA 0x24
/* Control Commands */
#define GPMC_CONFIG_RDY_BSY 0x00000001
#define GPMC_CONFIG_DEV_SIZE 0x00000002
#define GPMC_CONFIG_DEV_TYPE 0x00000003
#define GPMC_SET_IRQ_STATUS 0x00000004
#define GPMC_CONFIG_WP 0x00000005
#define GPMC_ENABLE_IRQ 0x0000000d
/* ECC commands */
#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
#define GPMC_CONFIG7_CSVALID (1 << 6)
#define GPMC_DEVICETYPE_NOR 0
#define GPMC_DEVICETYPE_NAND 2
#define GPMC_CONFIG_WRITEPROTECT 0x00000010
#define WR_RD_PIN_MONITORING 0x00600000
#define GPMC_IRQ_FIFOEVENTENABLE 0x01
#define GPMC_IRQ_COUNT_EVENT 0x02
#define GPMC_BURST_4 4 /* 4 word burst */
#define GPMC_BURST_8 8 /* 8 word burst */
#define GPMC_BURST_16 16 /* 16 word burst */
#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
/* bool type time settings */
struct gpmc_bool_timings {
bool cycle2cyclediffcsen;
bool cycle2cyclesamecsen;
bool we_extra_delay;
bool oe_extra_delay;
bool adv_extra_delay;
bool cs_extra_delay;
bool time_para_granularity;
};
/*
* Note that all values in this struct are in nanoseconds except sync_clk
* (which is in picoseconds), while the register values are in gpmc_fck cycles.
*/
struct gpmc_timings {
/* Minimum clock period for synchronous mode (in picoseconds) */
u32 sync_clk;
/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
u32 cs_on; /* Assertion time */
u32 cs_rd_off; /* Read deassertion time */
u32 cs_wr_off; /* Write deassertion time */
/* ADV signal timings corresponding to GPMC_CONFIG3 */
u32 adv_on; /* Assertion time */
u32 adv_rd_off; /* Read deassertion time */
u32 adv_wr_off; /* Write deassertion time */
/* WE signals timings corresponding to GPMC_CONFIG4 */
u32 we_on; /* WE assertion time */
u32 we_off; /* WE deassertion time */
/* OE signals timings corresponding to GPMC_CONFIG4 */
u32 oe_on; /* OE assertion time */
u32 oe_off; /* OE deassertion time */
/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
u32 page_burst_access; /* Multiple access word delay */
u32 access; /* Start-cycle to first data valid delay */
u32 rd_cycle; /* Total read cycle time */
u32 wr_cycle; /* Total write cycle time */
u32 bus_turnaround;
u32 cycle2cycle_delay;
u32 wait_monitoring;
u32 clk_activation;
/* The following are only on OMAP3430 */
u32 wr_access; /* WRACCESSTIME */
u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
struct gpmc_bool_timings bool_timings;
};
/* Device timings in picoseconds */
struct gpmc_device_timings {
u32 t_ceasu; /* address setup to CS valid */
u32 t_avdasu; /* address setup to ADV valid */
/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
* of tusb using these timings even for sync whilst
* ideally for adv_rd/(wr)_off it should have considered
* t_avdh instead. This indirectly necessitates r/w
* variations of t_avdp as it is possible to have one
* sync & other async
*/
u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
u32 t_avdp_w;
u32 t_aavdh; /* address hold time */
u32 t_oeasu; /* address setup to OE valid */
u32 t_aa; /* access time from ADV assertion */
u32 t_iaa; /* initial access time */
u32 t_oe; /* access time from OE assertion */
u32 t_ce; /* access time from CS asertion */
u32 t_rd_cycle; /* read cycle time */
u32 t_cez_r; /* read CS deassertion to high Z */
u32 t_cez_w; /* write CS deassertion to high Z */
u32 t_oez; /* OE deassertion to high Z */
u32 t_weasu; /* address setup to WE valid */
u32 t_wpl; /* write assertion time */
u32 t_wph; /* write deassertion time */
u32 t_wr_cycle; /* write cycle time */
u32 clk;
u32 t_bacc; /* burst access valid clock to output delay */
u32 t_ces; /* CS setup time to clk */
u32 t_avds; /* ADV setup time to clk */
u32 t_avdh; /* ADV hold time from clk */
u32 t_ach; /* address hold time from clk */
u32 t_rdyo; /* clk to ready valid */
u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
u32 t_ce_avd; /* CS on to ADV on delay */
/* XXX: check the possibility of combining
* cyc_aavhd_oe & cyc_aavdh_we
*/
u8 cyc_aavdh_oe;/* read address hold time in cycles */
u8 cyc_aavdh_we;/* write address hold time in cycles */
u8 cyc_oe; /* access time from OE assertion in cycles */
u8 cyc_wpl; /* write deassertion time in cycles */
u32 cyc_iaa; /* initial access time in cycles */
/* extra delays */
bool ce_xdelay;
bool avd_xdelay;
bool oe_xdelay;
bool we_xdelay;
};
struct gpmc_settings {
bool burst_wrap; /* enables wrap bursting */
bool burst_read; /* enables read page/burst mode */
bool burst_write; /* enables write page/burst mode */
bool device_nand; /* device is NAND */
bool sync_read; /* enables synchronous reads */
bool sync_write; /* enables synchronous writes */
bool wait_on_read; /* monitor wait on reads */
bool wait_on_write; /* monitor wait on writes */
u32 burst_len; /* page/burst length */
u32 device_width; /* device bus width (8 or 16 bit) */
u32 mux_add_data; /* multiplex address & data */
u32 wait_pin; /* wait-pin to be used */
};
extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
struct gpmc_settings *gpmc_s,
struct gpmc_device_timings *dev_t);
extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
extern int gpmc_get_client_irq(unsigned irq_config);
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
extern int gpmc_calc_divider(unsigned int sync_clk);
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
extern void gpmc_cs_free(int cs);
extern void omap3_gpmc_save_context(void);
extern void omap3_gpmc_restore_context(void);
extern int gpmc_configure(int cmd, int wval);
extern void gpmc_read_settings_dt(struct device_node *np,
struct gpmc_settings *p);
#endif
#include <linux/omap-gpmc.h>
arch/arm/mach-omap2/pm34xx.c
View file @ 1306b20d
......@@ -29,6 +29,7 @@
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/omap-dma.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_data/gpio-omap.h>
#include <trace/events/power.h>
......@@ -43,7 +44,6 @@
#include "common.h"
#include "cm3xxx.h"
#include "cm-regbits-34xx.h"
#include "gpmc.h"
#include "prm-regbits-34xx.h"
#include "prm3xxx.h"
#include "pm.h"
......
drivers/memory/Kconfig
View file @ 1306b20d
......@@ -41,6 +41,14 @@ config TI_EMIF
parameters and other settings during frequency, voltage and
temperature changes
config OMAP_GPMC
bool
help
This driver is for the General Purpose Memory Controller (GPMC)
present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
interfacing to a variety of asynchronous as well as synchronous
memory drives like NOR, NAND, OneNAND, SRAM.
config MVEBU_DEVBUS
bool "Marvell EBU Device Bus Controller"
default y
......
drivers/memory/Makefile
View file @ 1306b20d
......@@ -8,6 +8,7 @@ endif
obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o
obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
obj-$(CONFIG_TI_EMIF) += emif.o
obj-$(CONFIG_OMAP_GPMC) += omap-gpmc.o
obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
......
arch/arm/mach-omap2/gpmc.c → drivers/memory/omap-gpmc.c
View file @ 1306b20d
......@@ -29,19 +29,15 @@
#include <linux/of_address.h>
#include <linux/of_mtd.h>
#include <linux/of_device.h>
#include <linux/omap-gpmc.h>
#include <linux/mtd/nand.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include <asm/mach-types.h>
#include "soc.h"
#include "omap_device.h"
#include "gpmc.h"
#include "gpmc-nand.h"
#include "gpmc-onenand.h"
#define DEVICE_NAME "omap-gpmc"
/* GPMC register offsets */
......@@ -115,6 +111,60 @@
#define GPMC_NR_WAITPINS 4
#define GPMC_CS_CONFIG1 0x00
#define GPMC_CS_CONFIG2 0x04
#define GPMC_CS_CONFIG3 0x08
#define GPMC_CS_CONFIG4 0x0c
#define GPMC_CS_CONFIG5 0x10
#define GPMC_CS_CONFIG6 0x14
#define GPMC_CS_CONFIG7 0x18
#define GPMC_CS_NAND_COMMAND 0x1c
#define GPMC_CS_NAND_ADDRESS 0x20
#define GPMC_CS_NAND_DATA 0x24
/* Control Commands */
#define GPMC_CONFIG_RDY_BSY 0x00000001
#define GPMC_CONFIG_DEV_SIZE 0x00000002
#define GPMC_CONFIG_DEV_TYPE 0x00000003
#define GPMC_SET_IRQ_STATUS 0x00000004
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
#define GPMC_CONFIG7_CSVALID (1 << 6)
#define GPMC_DEVICETYPE_NOR 0
#define GPMC_DEVICETYPE_NAND 2
#define GPMC_CONFIG_WRITEPROTECT 0x00000010
#define WR_RD_PIN_MONITORING 0x00600000
#define GPMC_ENABLE_IRQ 0x0000000d
/* ECC commands */
#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
/* XXX: Only NAND irq has been considered,currently these are the only ones used
*/
#define GPMC_NR_IRQ 2
......@@ -1956,35 +2006,9 @@ static __exit void gpmc_exit(void)
}
omap_postcore_initcall(gpmc_init);
postcore_initcall(gpmc_init);
module_exit(gpmc_exit);
static int __init omap_gpmc_init(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
char *oh_name = "gpmc";
/*
* if the board boots up with a populated DT, do not
* manually add the device from this initcall
*/
if (of_have_populated_dt())
return -ENODEV;
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return -ENODEV;
}
pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
return PTR_RET(pdev);
}
omap_postcore_initcall(omap_gpmc_init);
static irqreturn_t gpmc_handle_irq(int irq, void *dev)
{
int i;
......
include/linux/omap-gpmc.h 0 → 100644
View file @ 1306b20d
/*
* OMAP GPMC (General Purpose Memory Controller) defines
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/* Maximum Number of Chip Selects */
#define GPMC_CS_NUM 8
#define GPMC_CONFIG_WP 0x00000005
#define GPMC_IRQ_FIFOEVENTENABLE 0x01
#define GPMC_IRQ_COUNT_EVENT 0x02
#define GPMC_BURST_4 4 /* 4 word burst */
#define GPMC_BURST_8 8 /* 8 word burst */
#define GPMC_BURST_16 16 /* 16 word burst */
#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
/* bool type time settings */
struct gpmc_bool_timings {
bool cycle2cyclediffcsen;
bool cycle2cyclesamecsen;
bool we_extra_delay;
bool oe_extra_delay;
bool adv_extra_delay;
bool cs_extra_delay;
bool time_para_granularity;
};
/*
* Note that all values in this struct are in nanoseconds except sync_clk
* (which is in picoseconds), while the register values are in gpmc_fck cycles.
*/
struct gpmc_timings {
/* Minimum clock period for synchronous mode (in picoseconds) */
u32 sync_clk;
/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
u32 cs_on; /* Assertion time */
u32 cs_rd_off; /* Read deassertion time */
u32 cs_wr_off; /* Write deassertion time */
/* ADV signal timings corresponding to GPMC_CONFIG3 */
u32 adv_on; /* Assertion time */
u32 adv_rd_off; /* Read deassertion time */
u32 adv_wr_off; /* Write deassertion time */
/* WE signals timings corresponding to GPMC_CONFIG4 */
u32 we_on; /* WE assertion time */
u32 we_off; /* WE deassertion time */
/* OE signals timings corresponding to GPMC_CONFIG4 */
u32 oe_on; /* OE assertion time */
u32 oe_off; /* OE deassertion time */
/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
u32 page_burst_access; /* Multiple access word delay */
u32 access; /* Start-cycle to first data valid delay */
u32 rd_cycle; /* Total read cycle time */
u32 wr_cycle; /* Total write cycle time */
u32 bus_turnaround;
u32 cycle2cycle_delay;
u32 wait_monitoring;
u32 clk_activation;
/* The following are only on OMAP3430 */
u32 wr_access; /* WRACCESSTIME */
u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
struct gpmc_bool_timings bool_timings;
};
/* Device timings in picoseconds */
struct gpmc_device_timings {
u32 t_ceasu; /* address setup to CS valid */
u32 t_avdasu; /* address setup to ADV valid */
/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
* of tusb using these timings even for sync whilst
* ideally for adv_rd/(wr)_off it should have considered
* t_avdh instead. This indirectly necessitates r/w
* variations of t_avdp as it is possible to have one
* sync & other async
*/
u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
u32 t_avdp_w;
u32 t_aavdh; /* address hold time */
u32 t_oeasu; /* address setup to OE valid */
u32 t_aa; /* access time from ADV assertion */
u32 t_iaa; /* initial access time */
u32 t_oe; /* access time from OE assertion */
u32 t_ce; /* access time from CS asertion */
u32 t_rd_cycle; /* read cycle time */
u32 t_cez_r; /* read CS deassertion to high Z */
u32 t_cez_w; /* write CS deassertion to high Z */
u32 t_oez; /* OE deassertion to high Z */
u32 t_weasu; /* address setup to WE valid */
u32 t_wpl; /* write assertion time */
u32 t_wph; /* write deassertion time */
u32 t_wr_cycle; /* write cycle time */
u32 clk;
u32 t_bacc; /* burst access valid clock to output delay */
u32 t_ces; /* CS setup time to clk */
u32 t_avds; /* ADV setup time to clk */
u32 t_avdh; /* ADV hold time from clk */
u32 t_ach; /* address hold time from clk */
u32 t_rdyo; /* clk to ready valid */
u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
u32 t_ce_avd; /* CS on to ADV on delay */
/* XXX: check the possibility of combining
* cyc_aavhd_oe & cyc_aavdh_we
*/
u8 cyc_aavdh_oe;/* read address hold time in cycles */
u8 cyc_aavdh_we;/* write address hold time in cycles */
u8 cyc_oe; /* access time from OE assertion in cycles */
u8 cyc_wpl; /* write deassertion time in cycles */
u32 cyc_iaa; /* initial access time in cycles */
/* extra delays */
bool ce_xdelay;
bool avd_xdelay;
bool oe_xdelay;
bool we_xdelay;
};
struct gpmc_settings {
bool burst_wrap; /* enables wrap bursting */
bool burst_read; /* enables read page/burst mode */
bool burst_write; /* enables write page/burst mode */
bool device_nand; /* device is NAND */
bool sync_read; /* enables synchronous reads */
bool sync_write; /* enables synchronous writes */
bool wait_on_read; /* monitor wait on reads */
bool wait_on_write; /* monitor wait on writes */
u32 burst_len; /* page/burst length */
u32 device_width; /* device bus width (8 or 16 bit) */
u32 mux_add_data; /* multiplex address & data */
u32 wait_pin; /* wait-pin to be used */
};
extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
struct gpmc_settings *gpmc_s,
struct gpmc_device_timings *dev_t);
struct gpmc_nand_regs;
struct device_node;
extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
extern int gpmc_get_client_irq(unsigned irq_config);
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
extern int gpmc_calc_divider(unsigned int sync_clk);
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
extern void gpmc_cs_free(int cs);
extern int gpmc_configure(int cmd, int wval);
extern void gpmc_read_settings_dt(struct device_node *np,
struct gpmc_settings *p);
extern void omap3_gpmc_save_context(void);
extern void omap3_gpmc_restore_context(void);
struct gpmc_timings;
struct omap_nand_platform_data;
struct omap_onenand_platform_data;
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
extern int gpmc_nand_init(struct omap_nand_platform_data *d,
struct gpmc_timings *gpmc_t);
#else
static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
struct gpmc_timings *gpmc_t)
{
return 0;
}
#endif
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
#else
#define board_onenand_data NULL
static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
{
}
#endif
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