Commit 13efd80a authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski

ARM: dts: exynos: Add GPU/Mali 400 node to Exynos4

Add nodes for GPU (Mali 400) to Exynos4210 and Exynos4412.  Describe the
GPU as much as possible however still few elements are missing:
1. Exynos4210 bus clock is not described in hardware manual therefore
   the IP gate clock was provided,
2. Exynos4412: Not sure what to do with CLK_G3D clock responsible for
   gating entire IP block (it is now being disabled as unused),
3. Regulator supplies on Trats board.

Limited testing on Odroid U3 (Exynos4412).
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 4a7bc07f
......@@ -51,6 +51,42 @@ aliases {
serial3 = &serial_3;
};
gpu: gpu@13000000 {
compatible = "samsung,exynos4210-mali", "arm,mali-400";
reg = <0x13000000 0x10000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pp2",
"ppmmu2",
"pp3",
"ppmmu3",
"pmu";
/*
* CLK_G3D is not actually bus clock but a IP-level clock.
* The bus clock is not described in hardware manual.
*/
clocks = <&clock CLK_G3D>,
<&clock CLK_SCLK_G3D>;
clock-names = "bus", "core";
power-domains = <&pd_g3d>;
status = "disabled";
};
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
......
......@@ -132,6 +132,11 @@ &fimd {
status = "okay";
};
&gpu {
mali-supply = <&buck3_reg>;
status = "okay";
};
&hsotg {
vusb_d-supply = <&ldo3_reg>;
vusb_a-supply = <&ldo8_reg>;
......
......@@ -239,6 +239,10 @@ &fimd {
status = "okay";
};
&gpu {
status = "okay";
};
&hsotg {
vusb_d-supply = <&vusb_reg>;
vusb_a-supply = <&vusbdac_reg>;
......
......@@ -262,6 +262,11 @@ fimd_dpi_ep: endpoint {
};
};
&gpu {
mali-supply = <&buck2_reg>;
status = "okay";
};
&hdmi {
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
......
......@@ -449,6 +449,23 @@ &fimc_3 {
samsung,lcd-wb;
};
&gpu {
operating-points-v2 = <&gpu_opp_table>;
gpu_opp_table: opp_table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <950000>;
};
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-microvolt = <1050000>;
};
};
};
&mdma1 {
power-domains = <&pd_lcd0>;
};
......
......@@ -115,6 +115,11 @@ &cpu0 {
cpu0-supply = <&buck2_reg>;
};
&gpu {
mali-supply = <&buck4_reg>;
status = "okay";
};
&hsotg {
vusb_d-supply = <&ldo15_reg>;
vusb_a-supply = <&ldo12_reg>;
......
......@@ -453,6 +453,11 @@ &fimd {
status = "okay";
};
&gpu {
mali-supply = <&buck4_reg>;
status = "okay";
};
&hdmi {
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
......
......@@ -229,6 +229,11 @@ &fimc_3 {
assigned-clock-rates = <0>, <176000000>;
};
&gpu {
mali-supply = <&buck4_reg>;
status = "okay";
};
&hdmi {
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
......
......@@ -38,3 +38,10 @@ &cooling_map1 {
cooling-device = <&cpu0 15 15>, <&cpu1 15 15>,
<&cpu2 15 15>, <&cpu3 15 15>;
};
&gpu_opp_table {
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1075000>;
};
};
......@@ -716,6 +716,31 @@ &gic {
cpu-offset = <0x4000>;
};
&gpu {
operating-points-v2 = <&gpu_opp_table>;
gpu_opp_table: opp_table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <875000>;
};
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-microvolt = <900000>;
};
opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <950000>;
};
opp-440000000 {
opp-hz = /bits/ 64 <440000000>;
opp-microvolt = <1025000>;
};
};
};
&hdmi {
compatible = "samsung,exynos4212-hdmi";
};
......
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