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Commit 1409f3fd authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'imx-dt-3.17' of... 

Merge tag 'imx-dt-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Merge "ARM: imx: device tree updates for 3.17" from Shawn Guo:

The i.MX device tree updates for 3.17:
 - Add device tree sources and pin function header for i.MX6SX SoC
 - Initial imx6sx-sdb board support with FEC, MMC, USB, PMIC, Audio
   and GPIO key enabled
 - New board support: mbimxsd25 and mbimxsd27 from Eukrea, aristainetos
   imx6dl boards, Rex Pro and Basic, Ka-Ro TX6
 - Restructure imx6qdl-wandboard.dtsi for new rev C1 board
 - Split M28EVK and M53EVK into SoM and EVK parts
 - A few correction around SDMA, SSI and SATA device nodes
 - Add eSATA support for Cubox-i board
 - Updates on edmqmx6 to enable PCIe, I2C and CAN
 - Use DT macro for clock ID for imx27 and imx6qdl
 - Add FlexCAN support for VF610 SoC

* tag 'imx-dt-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (125 commits)
  ARM: dts: vf610: add FlexCAN node
  ARM: dts: add initial Rex Basic board support
  ARM: dts: add initial Rex Pro board support
  ARM: dts: mx5: Split M53EVK into SoM and EVK parts
  ARM: dts: imx6: RIoTboard explicitly define pad settings
  ARM: dts: vf610: fix length of eshdc1 register property
  ARM: dts: Restructure imx6qdl-wandboard.dtsi for new rev C1 board.
  ARM: dts: imx53: correct clock-names of SATA node
  ARM: imx6: Align ssi nodes between mx6 variants
  ARM: i.MX27 clk: dts: Use clock defines in DTS files
  ARM: dts: imx: correct sdma compatbile for imx6sl and imx6sx
  ARM: dts: imx6sx-sdb: Add audio support
  ARM: dts: imx6sx: Pass the fsl,fifo-depth property
  ARM: dts: imx6sx: Fix sdma node
  ARM: dts: imx6: edmqmx6: Add can bus
  ARM: dts: imx6: edmqmx6: Add two other i2c buses
  ARM: dts: imx6: edmqmx6: Add PCIe support
  ARM: dts: imx25-pdk: Add USB OTG support
  ARM: dts: i.MX53: add aipstz nodes
  ARM: dts: mxs: Split M28EVK into SoM and EVK parts
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f097748f 69603fbb
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Showing with 9498 additions and 5034 deletions
Documentation/devicetree/bindings/clock/imx1-clock.txt 0 → 100644
View file @ 1409f3fd
* Clock bindings for Freescale i.MX1 CPUs
Required properties:
- compatible: Should be "fsl,imx1-ccm".
- reg: Address and length of the register set.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
for the full list of i.MX1 clock IDs.
Examples:
clks: ccm@0021b000 {
#clock-cells = <1>;
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};
pwm: pwm@00208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx21-clock.txt 0 → 100644
View file @ 1409f3fd
* Clock bindings for Freescale i.MX21
Required properties:
- compatible : Should be "fsl,imx21-ccm".
- reg : Address and length of the register set.
- interrupts : Should contain CCM interrupt.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
for the full list of i.MX21 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx21-ccm";
reg = <0x10027000 0x800>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
Documentation/devicetree/bindings/clock/imx27-clock.txt
View file @ 1409f3fd
......@@ -7,117 +7,22 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX27
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
mpll_main2 5
ahb 6
ipg 7
nfc_div 8
per1_div 9
per2_div 10
per3_div 11
per4_div 12
vpu_sel 13
vpu_div 14
usb_div 15
cpu_sel 16
clko_sel 17
cpu_div 18
clko_div 19
ssi1_sel 20
ssi2_sel 21
ssi1_div 22
ssi2_div 23
clko_en 24
ssi2_ipg_gate 25
ssi1_ipg_gate 26
slcdc_ipg_gate 27
sdhc3_ipg_gate 28
sdhc2_ipg_gate 29
sdhc1_ipg_gate 30
scc_ipg_gate 31
sahara_ipg_gate 32
rtc_ipg_gate 33
pwm_ipg_gate 34
owire_ipg_gate 35
lcdc_ipg_gate 36
kpp_ipg_gate 37
iim_ipg_gate 38
i2c2_ipg_gate 39
i2c1_ipg_gate 40
gpt6_ipg_gate 41
gpt5_ipg_gate 42
gpt4_ipg_gate 43
gpt3_ipg_gate 44
gpt2_ipg_gate 45
gpt1_ipg_gate 46
gpio_ipg_gate 47
fec_ipg_gate 48
emma_ipg_gate 49
dma_ipg_gate 50
cspi3_ipg_gate 51
cspi2_ipg_gate 52
cspi1_ipg_gate 53
nfc_baud_gate 54
ssi2_baud_gate 55
ssi1_baud_gate 56
vpu_baud_gate 57
per4_gate 58
per3_gate 59
per2_gate 60
per1_gate 61
usb_ahb_gate 62
slcdc_ahb_gate 63
sahara_ahb_gate 64
lcdc_ahb_gate 65
vpu_ahb_gate 66
fec_ahb_gate 67
emma_ahb_gate 68
emi_ahb_gate 69
dma_ahb_gate 70
csi_ahb_gate 71
brom_ahb_gate 72
ata_ahb_gate 73
wdog_ipg_gate 74
usb_ipg_gate 75
uart6_ipg_gate 76
uart5_ipg_gate 77
uart4_ipg_gate 78
uart3_ipg_gate 79
uart2_ipg_gate 80
uart1_ipg_gate 81
ckih_div1p5 82
fpm 83
mpll_osc_sel 84
mpll_sel 85
spll_gate 86
mshc_div 87
rtic_ipg_gate 88
mshc_ipg_gate 89
rtic_ahb_gate 90
mshc_baud_gate 91
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
for the full list of i.MX27 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks 81>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
Documentation/devicetree/bindings/clock/imx6q-clock.txt
View file @ 1409f3fd
......@@ -7,223 +7,13 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
clocks and IDs.
Clock ID
---------------------------
dummy 0
ckil 1
ckih 2
osc 3
pll2_pfd0_352m 4
pll2_pfd1_594m 5
pll2_pfd2_396m 6
pll3_pfd0_720m 7
pll3_pfd1_540m 8
pll3_pfd2_508m 9
pll3_pfd3_454m 10
pll2_198m 11
pll3_120m 12
pll3_80m 13
pll3_60m 14
twd 15
step 16
pll1_sw 17
periph_pre 18
periph2_pre 19
periph_clk2_sel 20
periph2_clk2_sel 21
axi_sel 22
esai_sel 23
asrc_sel 24
spdif_sel 25
gpu2d_axi 26
gpu3d_axi 27
gpu2d_core_sel 28
gpu3d_core_sel 29
gpu3d_shader_sel 30
ipu1_sel 31
ipu2_sel 32
ldb_di0_sel 33
ldb_di1_sel 34
ipu1_di0_pre_sel 35
ipu1_di1_pre_sel 36
ipu2_di0_pre_sel 37
ipu2_di1_pre_sel 38
ipu1_di0_sel 39
ipu1_di1_sel 40
ipu2_di0_sel 41
ipu2_di1_sel 42
hsi_tx_sel 43
pcie_axi_sel 44
ssi1_sel 45
ssi2_sel 46
ssi3_sel 47
usdhc1_sel 48
usdhc2_sel 49
usdhc3_sel 50
usdhc4_sel 51
enfc_sel 52
emi_sel 53
emi_slow_sel 54
vdo_axi_sel 55
vpu_axi_sel 56
cko1_sel 57
periph 58
periph2 59
periph_clk2 60
periph2_clk2 61
ipg 62
ipg_per 63
esai_pred 64
esai_podf 65
asrc_pred 66
asrc_podf 67
spdif_pred 68
spdif_podf 69
can_root 70
ecspi_root 71
gpu2d_core_podf 72
gpu3d_core_podf 73
gpu3d_shader 74
ipu1_podf 75
ipu2_podf 76
ldb_di0_podf 77
ldb_di1_podf 78
ipu1_di0_pre 79
ipu1_di1_pre 80
ipu2_di0_pre 81
ipu2_di1_pre 82
hsi_tx_podf 83
ssi1_pred 84
ssi1_podf 85
ssi2_pred 86
ssi2_podf 87
ssi3_pred 88
ssi3_podf 89
uart_serial_podf 90
usdhc1_podf 91
usdhc2_podf 92
usdhc3_podf 93
usdhc4_podf 94
enfc_pred 95
enfc_podf 96
emi_podf 97
emi_slow_podf 98
vpu_axi_podf 99
cko1_podf 100
axi 101
mmdc_ch0_axi_podf 102
mmdc_ch1_axi_podf 103
arm 104
ahb 105
apbh_dma 106
asrc 107
can1_ipg 108
can1_serial 109
can2_ipg 110
can2_serial 111
ecspi1 112
ecspi2 113
ecspi3 114
ecspi4 115
ecspi5 116
enet 117
esai 118
gpt_ipg 119
gpt_ipg_per 120
gpu2d_core 121
gpu3d_core 122
hdmi_iahb 123
hdmi_isfr 124
i2c1 125
i2c2 126
i2c3 127
iim 128
enfc 129
ipu1 130
ipu1_di0 131
ipu1_di1 132
ipu2 133
ipu2_di0 134
ldb_di0 135
ldb_di1 136
ipu2_di1 137
hsi_tx 138
mlb 139
mmdc_ch0_axi 140
mmdc_ch1_axi 141
ocram 142
openvg_axi 143
pcie_axi 144
pwm1 145
pwm2 146
pwm3 147
pwm4 148
per1_bch 149
gpmi_bch_apb 150
gpmi_bch 151
gpmi_io 152
gpmi_apb 153
sata 154
sdma 155
spba 156
ssi1 157
ssi2 158
ssi3 159
uart_ipg 160
uart_serial 161
usboh3 162
usdhc1 163
usdhc2 164
usdhc3 165
usdhc4 166
vdo_axi 167
vpu_axi 168
cko1 169
pll1_sys 170
pll2_bus 171
pll3_usb_otg 172
pll4_audio 173
pll5_video 174
pll8_mlb 175
pll7_usb_host 176
pll6_enet 177
ssi1_ipg 178
ssi2_ipg 179
ssi3_ipg 180
rom 181
usbphy1 182
usbphy2 183
ldb_di0_div_3_5 184
ldb_di1_div_3_5 185
sata_ref 186
sata_ref_100m 187
pcie_ref 188
pcie_ref_125m 189
enet_ref 190
usbphy1_gate 191
usbphy2_gate 192
pll4_post_div 193
pll5_post_div 194
pll5_video_div 195
eim_slow 196
spdif 197
cko2_sel 198
cko2_podf 199
cko2 200
cko 201
vdoa 202
pll4_audio_div 203
lvds1_sel 204
lvds2_sel 205
lvds1_gate 206
lvds2_gate 207
esai_ahb 208
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
for the full list of i.MX6 Quad and DualLite clock IDs.
Examples:
#include <dt-bindings/clock/imx6qdl-clock.h>
clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
......@@ -235,7 +25,7 @@ uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks 160>, <&clks 161>;
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
arch/arm/boot/dts/Makefile
View file @ 1409f3fd
......@@ -157,10 +157,14 @@ dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_MXC) += \
imx25-eukrea-mbimxsd25-baseboard.dtb \
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \
imx25-karo-tx25.dtb \
imx25-pdk.dtb \
imx27-apf27.dtb \
imx27-apf27dev.dtb \
imx27-eukrea-mbimxsd27-baseboard.dtb \
imx27-pdk.dtb \
imx27-phytec-phycore-rdk.dtb \
imx27-phytec-phycard-s-rdk.dtb \
......@@ -182,6 +186,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx53-tx53-x03x.dtb \
imx53-tx53-x13x.dtb \
imx53-voipac-bsb.dtb \
imx6dl-aristainetos_4.dtb \
imx6dl-aristainetos_7.dtb \
imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
......@@ -191,11 +197,16 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6dl-hummingboard.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \
imx6dl-tx6dl-comtft.dtb \
imx6dl-tx6u-801x.dtb \
imx6dl-tx6u-811x.dtb \
imx6dl-wandboard.dtb \
imx6dl-wandboard-revb1.dtb \
imx6q-arm2.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
......@@ -209,13 +220,21 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-gw54xx.dtb \
imx6q-nitrogen6x.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
imx6q-sbc6x.dtb \
imx6q-udoo.dtb \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
imx6q-tx6q-1010.dtb \
imx6q-tx6q-1010-comtft.dtb \
imx6q-tx6q-1020.dtb \
imx6q-tx6q-1020-comtft.dtb \
imx6q-tx6q-1110.dtb \
imx6sl-evk.dtb \
imx6sx-sdb.dtb \
vf610-colibri.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
......
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx25-eukrea-mbimxsd25-baseboard.dts"
/ {
model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
cmo_qvga: display {
model = "CMO-QVGA";
bits-per-pixel = <16>;
fsl,pcr = <0xcad08b80>;
bus-width = <18>;
native-mode = <&qvga_timings>;
display-timings {
qvga_timings: 320x240 {
clock-frequency = <6500000>;
hactive = <320>;
vactive = <240>;
hback-porch = <30>;
hfront-porch = <38>;
vback-porch = <20>;
vfront-porch = <3>;
hsync-len = <15>;
vsync-len = <4>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_lcd_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
};
&iomuxc {
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
};
};
};
&lcdc {
display = <&cmo_qvga>;
fsl,lpccr = <0x00a903ff>;
lcd-supply = <&reg_lcd_3v3>;
status = "okay";
};
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx25-eukrea-mbimxsd25-baseboard.dts"
/ {
model = "Eukrea MBIMXSD25 with the DVI-SVGA Display";
compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
dvi_svga: display {
model = "DVI-SVGA";
bits-per-pixel = <16>;
fsl,pcr = <0xfa208b80>;
bus-width = <18>;
native-mode = <&dvi_svga_timings>;
display-timings {
dvi_svga_timings: 800x600 {
clock-frequency = <40000000>;
hactive = <800>;
vactive = <600>;
hback-porch = <75>;
hfront-porch = <75>;
vback-porch = <7>;
vfront-porch = <75>;
hsync-len = <7>;
vsync-len = <7>;
};
};
};
};
&lcdc {
display = <&dvi_svga>;
status = "okay";
};
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx25-eukrea-mbimxsd25-baseboard.dts"
/ {
model = "Eukrea MBIMXSD25 with the DVI-VGA Display";
compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
dvi_vga: display {
model = "DVI-VGA";
bits-per-pixel = <16>;
fsl,pcr = <0xfa208b80>;
bus-width = <18>;
native-mode = <&dvi_vga_timings>;
display-timings {
dvi_vga_timings: 640x480 {
clock-frequency = <31250000>;
hactive = <640>;
vactive = <480>;
hback-porch = <100>;
hfront-porch = <100>;
vback-porch = <7>;
vfront-porch = <100>;
hsync-len = <7>;
vsync-len = <7>;
};
};
};
};
&lcdc {
display = <&dvi_vga>;
status = "okay";
};
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
View file @ 1409f3fd
......@@ -155,7 +155,6 @@ MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
&ssi1 {
codec-handle = <&tlv320aic23>;
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx25-pdk.dts
View file @ 1409f3fd
......@@ -233,7 +233,6 @@ MATRIX_KEY(0x3, 0x2, KEY_POWER)
&ssi1 {
codec-handle = <&codec>;
fsl,mode = "i2s-slave";
status = "okay";
};
......@@ -249,3 +248,10 @@ &usbhost1 {
dr_mode = "host";
status = "okay";
};
&usbotg {
phy_type = "utmi";
dr_mode = "otg";
external-vbus-divider;
status = "okay";
};
arch/arm/boot/dts/imx25.dtsi
View file @ 1409f3fd
......@@ -312,7 +312,7 @@ clks: ccm@53f80000 {
gpt4: timer@53f84000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f84000 0x4000>;
clocks = <&clks 9>, <&clks 45>;
clocks = <&clks 95>, <&clks 47>;
clock-names = "ipg", "per";
interrupts = <1>;
};
......@@ -320,7 +320,7 @@ gpt4: timer@53f84000 {
gpt3: timer@53f88000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f88000 0x4000>;
clocks = <&clks 9>, <&clks 47>;
clocks = <&clks 94>, <&clks 47>;
clock-names = "ipg", "per";
interrupts = <29>;
};
......@@ -328,7 +328,7 @@ gpt3: timer@53f88000 {
gpt2: timer@53f8c000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f8c000 0x4000>;
clocks = <&clks 9>, <&clks 47>;
clocks = <&clks 93>, <&clks 47>;
clock-names = "ipg", "per";
interrupts = <53>;
};
......@@ -336,7 +336,7 @@ gpt2: timer@53f8c000 {
gpt1: timer@53f90000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f90000 0x4000>;
clocks = <&clks 9>, <&clks 47>;
clocks = <&clks 92>, <&clks 47>;
clock-names = "ipg", "per";
interrupts = <54>;
};
......
arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi 0 → 100644
View file @ 1409f3fd
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx27.dtsi"
/ {
model = "Eukrea CPUIMX27";
compatible = "eukrea,cpuimx27", "fsl,imx27";
memory {
reg = <0xa0000000 0x04000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-bus";
clk14745600: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
reg = <0>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};
&owire {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire>;
status = "okay";
};
&sdhci2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhc2>;
bus-width = <4>;
non-removable;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbh2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh2>;
dr_mode = "host";
phy_type = "ulpi";
disable-over-current;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg";
phy_type = "ulpi";
disable-over-current;
status = "okay";
};
&weim {
status = "okay";
nor: nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
linux,mtd-name = "physmap-flash.0";
fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
};
uart8250@3,200000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_1>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x200000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
no-loopback-test;
};
uart8250@3,400000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_2>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x400000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
no-loopback-test;
};
uart8250@3,800000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_3>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x800000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
no-loopback-test;
};
uart8250@3,1000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_4>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x1000000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
no-loopback-test;
};
};
&iomuxc {
imx27-eukrea-cpuimx27 {
pinctrl_fec: fecgrp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_owire: owiregrp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
MX27_PAD_USBH1_FS__UART4_RTS 0x0
>;
};
pinctrl_uart8250_1: uart82501grp {
fsl,pins = <
MX27_PAD_USB_PWR__GPIO2_23 0x0
>;
};
pinctrl_uart8250_2: uart82502grp {
fsl,pins = <
MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
>;
};
pinctrl_uart8250_3: uart82503grp {
fsl,pins = <
MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
>;
};
pinctrl_uart8250_4: uart82504grp {
fsl,pins = <
MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
MX27_PAD_USBH2_STP__USBH2_STP 0x0
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
};
};
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx27-eukrea-cpuimx27.dtsi"
/ {
model = "Eukrea MBIMXSD27";
compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27";
display0: CMO-QVGA {
model = "CMO-QVGA";
native-mode = <&timing0>;
bits-per-pixel = <16>;
fsl,pcr = <0xfad08b80>;
display-timings {
timing0: 320x240 {
clock-frequency = <6500000>;
hactive = <320>;
vactive = <240>;
hback-porch = <20>;
hsync-len = <30>;
hfront-porch = <38>;
vback-porch = <4>;
vsync-len = <3>;
vfront-porch = <15>;
};
};
};
backlight {
compatible = "gpio-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioleds>;
led1 {
label = "system::live";
gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "system::user";
gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
};
};
regulators {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-bus";
reg_lcd: regulator@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdreg>;
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "LCD";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
};
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
status = "okay";
ads7846 {
compatible = "ti,ads7846";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
reg = <0>;
interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
spi-cpol;
spi-max-frequency = <1500000>;
ti,keep-vref-on;
};
};
&fb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imxfb>;
display = <&display0>;
lcd-supply = <&reg_lcd>;
fsl,dmacr = <0x00040060>;
fsl,lscr1 = <0x00120300>;
fsl,lpccr = <0x00a903ff>;
status = "okay";
};
&i2c1 {
codec: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
};
};
&kpp {
linux,keymap = <
MATRIX_KEY(0, 0, KEY_UP)
MATRIX_KEY(0, 1, KEY_DOWN)
MATRIX_KEY(1, 0, KEY_RIGHT)
MATRIX_KEY(1, 1, KEY_LEFT)
>;
status = "okay";
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhc1>;
bus-width = <4>;
status = "okay";
};
&ssi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssi1>;
codec-handle = <&codec>;
status = "okay";
};
&uart1 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&iomuxc {
imx27-eukrea-cpuimx27-baseboard {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX27_PAD_PWMO__GPIO5_5 0x0
>;
};
pinctrl_gpioleds: gpioledsgrp {
fsl,pins = <
MX27_PAD_PC_PWRON__GPIO6_16 0x0
MX27_PAD_PC_CD2_B__GPIO6_19 0x0
>;
};
pinctrl_imxfb: imxfbgrp {
fsl,pins = <
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_lcdreg: lcdreggrp {
fsl,pins = <
MX27_PAD_CLS__GPIO1_25 0x0
>;
};
pinctrl_sdhc1: sdhc1grp {
fsl,pins = <
MX27_PAD_SD1_CLK__SD1_CLK 0x0
MX27_PAD_SD1_CMD__SD1_CMD 0x0
MX27_PAD_SD1_D0__SD1_D0 0x0
MX27_PAD_SD1_D1__SD1_D1 0x0
MX27_PAD_SD1_D2__SD1_D2 0x0
MX27_PAD_SD1_D3__SD1_D3 0x0
>;
};
pinctrl_ssi1: ssi1grp {
fsl,pins = <
MX27_PAD_SSI4_CLK__SSI4_CLK 0x0
MX27_PAD_SSI4_FS__SSI4_FS 0x0
MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1
MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_PAD_UART3_TXD__UART3_TXD 0x0
MX27_PAD_UART3_RXD__UART3_RXD 0x0
MX27_PAD_UART3_CTS__UART3_CTS 0x0
MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
};
};
arch/arm/boot/dts/imx27-pdk.dts
View file @ 1409f3fd
......@@ -28,7 +28,7 @@ usbphy {
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
clocks = <&clks 0>;
clocks = <&clks IMX27_CLK_DUMMY>;
clock-names = "main_clk";
};
};
......
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
View file @ 1409f3fd
......@@ -61,7 +61,7 @@ usbphy2: usbphy@2 {
compatible = "usb-nop-xceiv";
reg = <2>;
vcc-supply = <&reg_5v0>;
clocks = <&clks 0>;
clocks = <&clks IMX27_CLK_DUMMY>;
clock-names = "main_clk";
};
};
......
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
View file @ 1409f3fd
......@@ -51,7 +51,7 @@ usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
vcc-supply = <&sw3_reg>;
clocks = <&clks 0>;
clocks = <&clks IMX27_CLK_DUMMY>;
clock-names = "main_clk";
};
};
......@@ -310,7 +310,6 @@ &nfc {
&ssi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssi1>;
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx27.dtsi
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx28-cfa10036.dts
View file @ 1409f3fd
......@@ -53,6 +53,17 @@ MX28_PAD_GPMI_RDY0__USB0_ID
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 {
reg = <0>;
fsl,pinmux-ids = <
0x31c3 /*
MX28_PAD_PWM3__GPIO_3_28 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
};
ssp0: ssp@80010000 {
......@@ -60,6 +71,7 @@ ssp0: ssp@80010000 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a
&mmc0_cd_cfg &mmc0_sck_cfg>;
vmmc-supply = <&reg_vddio_sd0>;
bus-width = <4>;
status = "okay";
};
......@@ -116,4 +128,14 @@ power {
default-state = "on";
};
};
reg_vddio_sd0: vddio-sd0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pwr_cfa10036>;
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 28 0>;
};
};
arch/arm/boot/dts/imx28-m28.dtsi 0 → 100644
View file @ 1409f3fd
/*
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx28.dtsi"
/ {
model = "DENX M28";
compatible = "denx,m28", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
};
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";
partition@0 {
label = "bootloader";
reg = <0x00000000 0x00300000>;
read-only;
};
partition@1 {
label = "environment";
reg = <0x00300000 0x00080000>;
};
partition@2 {
label = "redundant-environment";
reg = <0x00380000 0x00080000>;
};
partition@3 {
label = "kernel";
reg = <0x00400000 0x00400000>;
};
partition@4 {
label = "filesystem";
reg = <0x00800000 0x0f800000>;
};
};
};
apbx@80040000 {
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
rtc: rtc@68 {
compatible = "stm,m41t62";
reg = <0x68>;
};
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
arch/arm/boot/dts/imx28-m28evk.dts
View file @ 1409f3fd
......@@ -10,52 +10,14 @@
*/
/dts-v1/;
#include "imx28.dtsi"
#include "imx28-m28.dtsi"
/ {
model = "DENX M28EVK";
compatible = "denx,m28evk", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
};
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";
partition@0 {
label = "bootloader";
reg = <0x00000000 0x00300000>;
read-only;
};
partition@1 {
label = "environment";
reg = <0x00300000 0x00080000>;
};
partition@2 {
label = "redundant-environment";
reg = <0x00380000 0x00080000>;
};
partition@3 {
label = "kernel";
reg = <0x00400000 0x00400000>;
};
partition@4 {
label = "filesystem";
reg = <0x00800000 0x0f800000>;
};
};
ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
......@@ -175,10 +137,6 @@ saif1: saif@80046000 {
};
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
......@@ -192,11 +150,6 @@ eeprom: eeprom@51 {
reg = <0x51>;
pagesize = <32>;
};
rtc: rtc@68 {
compatible = "stm,m41t62";
reg = <0x68>;
};
};
lradc@80050000 {
......@@ -284,19 +237,6 @@ backlight {
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vddio_sd0: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
......
arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
View file @ 1409f3fd
......@@ -133,7 +133,6 @@ MX35_PAD_CTS2__UART2_CTS 0x1c5
&ssi1 {
codec-handle = <&tlv320aic23>;
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx35.dtsi
View file @ 1409f3fd
......@@ -193,6 +193,14 @@ clks: ccm@53f80000 {
#clock-cells = <1>;
};
gpt: timer@53f90000 {
compatible = "fsl,imx35-gpt", "fsl,imx31-gpt";
reg = <0x53f90000 0x4000>;
interrupts = <29>;
clocks = <&clks 9>, <&clks 50>;
clock-names = "ipg", "per";
};
gpio3: gpio@53fa4000 {
compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
reg = <0x53fa4000 0x4000>;
......
arch/arm/boot/dts/imx50.dtsi
View file @ 1409f3fd
......@@ -151,8 +151,10 @@ ssi2: ssi@50014000 {
reg = <0x50014000 0x4000>;
interrupts = <30>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......@@ -457,8 +459,10 @@ ssi1: ssi@63fcc000 {
reg = <0x63fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......
arch/arm/boot/dts/imx51-babbage.dts
View file @ 1409f3fd
......@@ -203,6 +203,7 @@ pmic: mc13892@0 {
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
fsl,mc13xxx-uses-rtc;
regulators {
sw1_reg: sw1 {
......@@ -392,7 +393,6 @@ MATRIX_KEY(3, 3, KEY_POWER)
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
View file @ 1409f3fd
......@@ -255,7 +255,6 @@ MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
&ssi2 {
codec-handle = <&tlv320aic23>;
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx51.dtsi
View file @ 1409f3fd
......@@ -218,7 +218,6 @@ ssi2: ssi@70014000 {
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......@@ -508,7 +507,6 @@ ssi1: ssi@83fcc000 {
<&sdma 29 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......@@ -564,7 +562,6 @@ ssi3: ssi@83fe8000 {
<&sdma 47 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......
arch/arm/boot/dts/imx53-m53.dtsi 0 → 100644
View file @ 1409f3fd
/*
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx53.dtsi"
/ {
model = "DENX M53";
compatible = "denx,imx53-m53", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p2v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_backlight: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "lcd-supply";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "okay";
stmpe610@41 {
compatible = "st,stmpe610";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
id = <0>;
blocks = <0x5>;
interrupts = <6 0x0>;
interrupt-parent = <&gpio7>;
irq-trigger = <0x1>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
reg = <0>;
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <3>;
st,touch-det-delay = <3>;
st,settling = <4>;
st,fraction-z = <7>;
st,i-drive = <1>;
};
};
eeprom: eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
pagesize = <32>;
};
rtc: rtc@68 {
compatible = "stm,m41t62";
reg = <0x68>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx53-m53evk {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
>;
};
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};
arch/arm/boot/dts/imx53-m53evk.dts
View file @ 1409f3fd
......@@ -10,17 +10,12 @@
*/
/dts-v1/;
#include "imx53.dtsi"
#include "imx53-m53.dtsi"
/ {
model = "DENX M53EVK";
compatible = "denx,imx53-m53evk", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "bgr666";
......@@ -81,25 +76,6 @@ regulators {
#address-cells = <1>;
#size-cells = <0>;
reg_3p2v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_backlight: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "lcd-supply";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usbh1_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
......@@ -174,50 +150,6 @@ sgtl5000: codec@0a {
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "okay";
stmpe610@41 {
compatible = "st,stmpe610";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
id = <0>;
blocks = <0x5>;
interrupts = <6 0x0>;
interrupt-parent = <&gpio7>;
irq-trigger = <0x1>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
reg = <0>;
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <3>;
st,touch-det-delay = <3>;
st,settling = <4>;
st,fraction-z = <7>;
st,i-drive = <1>;
};
};
eeprom: eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
pagesize = <32>;
};
rtc: rtc@68 {
compatible = "stm,m41t62";
reg = <0x68>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
......@@ -229,11 +161,8 @@ &iomuxc {
pinctrl-0 = <&pinctrl_hog>;
imx53-m53evk {
pinctrl_hog: hoggrp {
pinctrl_usb: usbgrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_GPIO_2__GPIO1_2 0x80000000
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
>;
......@@ -302,13 +231,6 @@ MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
......@@ -353,26 +275,6 @@ MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
......@@ -408,14 +310,6 @@ &ipu_di1_disp1 {
remote-endpoint = <&display1_in>;
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
......@@ -427,7 +321,6 @@ &sata {
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
......@@ -450,6 +343,8 @@ &uart3 {
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb>;
vbus-supply = <&reg_usbh1_vbus>;
phy_type = "utmi";
status = "okay";
......
arch/arm/boot/dts/imx53-mba53.dts
View file @ 1409f3fd
......@@ -225,7 +225,6 @@ &uart1 {
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx53-qsb-common.dtsi
View file @ 1409f3fd
......@@ -141,7 +141,6 @@ &ipu_di0_disp0 {
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx53-tx53.dtsi
View file @ 1409f3fd
......@@ -502,7 +502,6 @@ &sdma {
};
&ssi1 {
fsl,mode = "i2s-slave";
codec-handle = <&sgtl5000>;
status = "okay";
};
......
arch/arm/boot/dts/imx53-voipac-bsb.dts
View file @ 1409f3fd
......@@ -154,6 +154,5 @@ &kpp {
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
arch/arm/boot/dts/imx53.dtsi
View file @ 1409f3fd
......@@ -108,7 +108,7 @@ sata: sata@10000000 {
clocks = <&clks IMX5_CLK_SATA_GATE>,
<&clks IMX5_CLK_SATA_REF>,
<&clks IMX5_CLK_AHB>;
clock-names = "sata_gate", "sata_ref", "ahb";
clock-names = "sata", "sata_ref", "ahb";
status = "disabled";
};
......@@ -231,7 +231,6 @@ ssi2: ssi@50014000 {
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......@@ -260,6 +259,11 @@ esdhc4: esdhc@50024000 {
};
};
aipstz1: bridge@53f00000 {
compatible = "fsl,imx53-aipstz";
reg = <0x53f00000 0x60>;
};
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
......@@ -572,6 +576,11 @@ aips@60000000 { /* AIPS2 */
reg = <0x60000000 0x10000000>;
ranges;
aipstz2: bridge@63f00000 {
compatible = "fsl,imx53-aipstz";
reg = <0x63f00000 0x60>;
};
iim: iim@63f98000 {
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
reg = <0x63f98000 0x4000>;
......@@ -661,7 +670,6 @@ ssi1: ssi@63fcc000 {
<&sdma 29 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......@@ -689,7 +697,6 @@ ssi3: ssi@63fe8000 {
<&sdma 47 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
......
arch/arm/boot/dts/imx6dl-aristainetos_4.dts 0 → 100644
View file @ 1409f3fd
/*
* support fot the imx6 based aristainetos board
*
* Copyright (C) 2014 Heiko Schocher <hs@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-aristainetos.dtsi"
/ {
model = "aristainetos i.MX6 Dual Lite Board 4";
compatible = "fsl,imx6dl";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
status = "okay";
};
memory {
reg = <0x10000000 0x40000000>;
};
soc {
display0: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp>;
status = "okay";
display-timings {
480x800p60 {
native-mode;
clock-frequency = <30000000>;
hactive = <480>;
vactive = <800>;
hfront-porch = <59>;
hback-porch = <10>;
hsync-len = <10>;
vback-porch = <15>;
vfront-porch = <15>;
vsync-len = <15>;
hsync-active = <1>;
vsync-active = <1>;
};
};
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
};
};
};
&ecspi2 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
arch/arm/boot/dts/imx6dl-aristainetos_7.dts 0 → 100644
View file @ 1409f3fd
/*
* support fot the imx6 based aristainetos board
*
* Copyright (C) 2014 Heiko Schocher <hs@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-aristainetos.dtsi"
/ {
model = "aristainetos i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl";
memory {
reg = <0x10000000 0x40000000>;
};
soc {
display0: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp>;
status = "okay";
display-timings {
800x480p60 {
native-mode;
clock-frequency = <33246000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <88>;
hback-porch = <88>;
hsync-len = <80>;
vback-porch = <10>;
vfront-porch = <10>;
vsync-len = <25>;
vsync-active = <1>;
};
};
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
};
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 3000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
arch/arm/boot/dts/imx6dl-gw51xx.dts
View file @ 1409f3fd
......@@ -14,6 +14,6 @@
#include "imx6qdl-gw51xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite GW51XX";
model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX";
compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl-gw52xx.dts
View file @ 1409f3fd
......@@ -14,6 +14,6 @@
#include "imx6qdl-gw52xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite GW52XX";
model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl-gw53xx.dts
View file @ 1409f3fd
......@@ -14,6 +14,6 @@
#include "imx6qdl-gw53xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite GW53XX";
model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl-gw54xx.dts
View file @ 1409f3fd
......@@ -14,6 +14,6 @@
#include "imx6qdl-gw54xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite GW54XX";
model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl-rex-basic.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 FEDEVEL, Inc.
*
* Author: Robert Nelson <robertcnelson@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-rex.dtsi"
/ {
model = "Rex Basic i.MX6 Dual Lite Board";
compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
memory {
reg = <0x10000000 0x20000000>;
};
};
&ecspi3 {
flash: m25p80@0 {
compatible = "sst,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
arch/arm/boot/dts/imx6dl-riotboard.dts
View file @ 1409f3fd
......@@ -254,7 +254,6 @@ &pwm4 {
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
......@@ -335,10 +334,10 @@ &iomuxc {
imx6-riotboard {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
>;
};
......@@ -376,7 +375,7 @@ pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
......@@ -389,9 +388,9 @@ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pu
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
......@@ -426,8 +425,8 @@ MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
pinctrl_led: ledgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
>;
};
......@@ -493,8 +492,8 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
>;
};
......@@ -506,8 +505,8 @@ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
>;
};
......@@ -519,8 +518,8 @@ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
>;
};
......@@ -532,7 +531,7 @@ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
>;
};
};
......
arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6DL Module on CoMpact TFT";
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 0>;
power-supply = <&reg_3v3>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_1>;
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
native-mode = <&ET070001DM6>;
ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&can1 {
status = "disabled";
};
&can2 {
xceiver-supply = <&reg_3v3>;
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&kpp {
status = "disabled";
};
&reg_can_xcvr {
status = "disabled";
};
&touchscreen {
status = "disabled";
};
arch/arm/boot/dts/imx6dl-tx6u-801x.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6U-801x Module";
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_3v3>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_1>;
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
arch/arm/boot/dts/imx6dl-tx6u-811x.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6U-811x Module";
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
aliases {
display = &lvds0;
lvds0 = &lvds0;
lvds1 = &lvds1;
};
backlight0: backlight0 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 0>;
power-supply = <&reg_lcd0_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
backlight1: backlight1 {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500000 0>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
};
&i2c3 {
polytouch2: eeti@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eeti>;
interrupt-parent = <&gpio3>;
interrupts = <22 0>;
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
linux,wakeup;
};
};
&iomuxc {
imx6dl-tx6u-811x {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};
};
&kpp {
status = "disabled"; /* pad conflict with backlight1 PWM */
};
&ldb {
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&lvds_timing0>;
lvds_timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
lvds1: lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "disabled";
display-timings {
native-mode = <&lvds_timing1>;
lvds_timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&pwm1 {
status = "okay";
};
arch/arm/mach-imx/mx1-camera-fiq-ksym.c → arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
View file @ 1409f3fd
/*
* Exported ksyms of ARCH_MX1
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com>
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-wandboard-revb1.dtsi"
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/platform_data/camera-mx1.h>
/ {
model = "Wandboard i.MX6 Dual Lite Board";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
/* IMX camera FIQ handler */
EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
EXPORT_SYMBOL(mx1_camera_sof_fiq_end);
memory {
reg = <0x10000000 0x40000000>;
};
};
arch/arm/boot/dts/imx6dl-wandboard.dts
View file @ 1409f3fd
......@@ -10,7 +10,7 @@
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-wandboard.dtsi"
#include "imx6qdl-wandboard-revc1.dtsi"
/ {
model = "Wandboard i.MX6 Dual Lite Board";
......
arch/arm/boot/dts/imx6dl.dtsi
View file @ 1409f3fd
......@@ -35,8 +35,11 @@ cpu@0 {
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
<&clks 17>, <&clks 170>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
......@@ -56,7 +59,7 @@ soc {
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks 142>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips1: aips-bus@02000000 {
......@@ -87,7 +90,7 @@ i2c4: i2c@021f8000 {
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 116>;
clocks = <&clks IMX6DL_CLK_I2C4>;
status = "disabled";
};
};
......@@ -104,9 +107,9 @@ &hdmi {
};
&ldb {
clocks = <&clks 33>, <&clks 34>,
<&clks 39>, <&clks 40>,
<&clks 135>, <&clks 136>;
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
......
arch/arm/boot/dts/imx6q-cubox-i.dts
View file @ 1409f3fd
......@@ -13,4 +13,8 @@ / {
&sata {
status = "okay";
fsl,transmit-level-mV = <1104>;
fsl,transmit-boost-mdB = <0>;
fsl,transmit-atten-16ths = <9>;
fsl,no-spread-spectrum;
};
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
View file @ 1409f3fd
......@@ -95,6 +95,12 @@ led-red {
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&ecspi5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
......@@ -118,6 +124,13 @@ &fec {
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
......@@ -274,6 +287,13 @@ rtc: m41t62@68 {
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
......@@ -286,6 +306,13 @@ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
>;
};
pinctrl_ecspi5: ecspi5rp-1 {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
......@@ -316,6 +343,13 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
......@@ -323,6 +357,19 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
>;
};
pinctrl_pfuze: pfuze100grp1 {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
......@@ -385,6 +432,13 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 8 0>;
status = "okay";
};
&sata {
status = "okay";
};
......
arch/arm/boot/dts/imx6q-gw51xx.dts
View file @ 1409f3fd
......@@ -14,6 +14,6 @@
#include "imx6qdl-gw51xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Quad GW51XX";
model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX";
compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q";
};
arch/arm/boot/dts/imx6q-gw52xx.dts
View file @ 1409f3fd
......@@ -14,7 +14,7 @@
#include "imx6qdl-gw52xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Quad GW52XX";
model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX";
compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
};
......
arch/arm/boot/dts/imx6q-gw53xx.dts
View file @ 1409f3fd
......@@ -14,7 +14,7 @@
#include "imx6qdl-gw53xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Quad GW53XX";
model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX";
compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
};
......
arch/arm/boot/dts/imx6q-gw5400-a.dts
View file @ 1409f3fd
......@@ -115,9 +115,9 @@ reg_usb_otg_vbus: regulator@3 {
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
......@@ -504,7 +504,6 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx6q-gw54xx.dts
View file @ 1409f3fd
......@@ -14,7 +14,7 @@
#include "imx6qdl-gw54xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Quad GW54XX";
model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
};
......
arch/arm/boot/dts/imx6q-rex-pro.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 FEDEVEL, Inc.
*
* Author: Robert Nelson <robertcnelson@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-rex.dtsi"
/ {
model = "Rex Pro i.MX6 Quad Board";
compatible = "rex,imx6q-rex-pro", "fsl,imx6q";
memory {
reg = <0x10000000 0x80000000>;
};
};
&ecspi3 {
flash: m25p80@0 {
compatible = "sst,sst25vf032b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&sata {
status = "okay";
};
arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT";
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 0>;
power-supply = <&reg_3v3>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_1>;
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
native-mode = <&ET070001DM6>;
ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&can1 {
status = "disabled";
};
&can2 {
xceiver-supply = <&reg_3v3>;
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&kpp {
status = "disabled";
};
&reg_can_xcvr {
status = "disabled";
};
&touchscreen {
status = "disabled";
};
arch/arm/boot/dts/imx6q-tx6q-1010.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6Q-1010 Module";
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_3v3>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_1>;
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT";
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 0>;
power-supply = <&reg_3v3>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_1>;
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
native-mode = <&ET070001DM6>;
ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&can1 {
status = "disabled";
};
&can2 {
xceiver-supply = <&reg_3v3>;
};
&ds1339 {
status = "disabled";
};
&gpmi {
status = "disabled";
};
&iomuxc {
imx6qdl-tx6 {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&kpp {
status = "disabled";
};
&reg_can_xcvr {
status = "disabled";
};
&touchscreen {
status = "disabled";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
no-1-8-v;
fsl,wp-controller;
status = "okay";
};
arch/arm/boot/dts/imx6q-tx6q-1020.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6Q-1020 Module";
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_3v3>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_1>;
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&ds1339 {
status = "disabled";
};
&gpmi {
status = "disabled";
};
&iomuxc {
imx6qdl-tx6 {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
no-1-8-v;
fsl,wp-controller;
status = "okay";
};
arch/arm/boot/dts/imx6q-tx6q-1110.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6Q-1110 Module";
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
aliases {
display = &lvds0;
lvds0 = &lvds0;
lvds1 = &lvds1;
};
backlight0: backlight0 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 0>;
power-supply = <&reg_lcd0_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
backlight1: backlight1 {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500000 0>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
};
&i2c3 {
polytouch1: eeti@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eeti>;
interrupt-parent = <&gpio3>;
interrupts = <22 0>;
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
linux,wakeup;
};
};
&iomuxc {
imx6q-tx6q-1110 {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};
};
&kpp {
status = "disabled"; /* pad conflict with backlight1 PWM */
};
&ldb {
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&lvds_timing0>;
lvds_timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
lvds1: lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "disabled";
display-timings {
native-mode = <&lvds_timing1>;
lvds_timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&pwm1 {
status = "okay";
};
&sata {
status = "okay";
};
arch/arm/boot/dts/imx6q-udoo.dts
View file @ 1409f3fd
......@@ -23,6 +23,23 @@ chosen {
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_h1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
gpio = <&gpio7 12 0>;
};
};
};
&fec {
......@@ -81,6 +98,13 @@ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh: usbhgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
......@@ -104,6 +128,14 @@ &uart2 {
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh>;
vbus-supply = <&reg_usb_h1_vbus>;
clocks = <&clks 201>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
......
arch/arm/boot/dts/imx6q-wandboard-revb1.dts 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-wandboard-revb1.dtsi"
/ {
model = "Wandboard i.MX6 Quad Board";
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
memory {
reg = <0x10000000 0x80000000>;
};
};
&sata {
status = "okay";
};
arch/arm/boot/dts/imx6q-wandboard.dts
View file @ 1409f3fd
......@@ -10,7 +10,7 @@
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-wandboard.dtsi"
#include "imx6qdl-wandboard-revc1.dtsi"
/ {
model = "Wandboard i.MX6 Quad Board";
......
arch/arm/boot/dts/imx6q.dtsi
View file @ 1409f3fd
......@@ -43,8 +43,11 @@ cpu@0 {
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
<&clks 17>, <&clks 170>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
......@@ -78,7 +81,7 @@ soc {
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
clocks = <&clks 142>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips-bus@02000000 { /* AIPS1 */
......@@ -89,7 +92,8 @@ ecspi5: ecspi@02018000 {
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02018000 0x4000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 116>, <&clks 116>;
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
status = "disabled";
};
......@@ -140,7 +144,9 @@ sata: sata@02200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 154>, <&clks 187>, <&clks 105>;
clocks = <&clks IMX6QDL_CLK_SATA>,
<&clks IMX6QDL_CLK_SATA_REF_100M>,
<&clks IMX6QDL_CLK_AHB>;
clock-names = "sata", "sata_ref", "ahb";
status = "disabled";
};
......@@ -152,10 +158,20 @@ ipu2: ipu@02800000 {
reg = <0x02800000 0x400000>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
<0 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
clocks = <&clks IMX6QDL_CLK_IPU2>,
<&clks IMX6QDL_CLK_IPU2_DI0>,
<&clks IMX6QDL_CLK_IPU2_DI1>;
clock-names = "bus", "di0", "di1";
resets = <&src 4>;
ipu2_csi0: port@0 {
reg = <0>;
};
ipu2_csi1: port@1 {
reg = <1>;
};
ipu2_di0: port@2 {
#address-cells = <1>;
#size-cells = <0>;
......@@ -230,9 +246,10 @@ hdmi_mux_3: endpoint {
};
&ldb {
clocks = <&clks 33>, <&clks 34>,
<&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
<&clks 135>, <&clks 136>;
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
"di0", "di1";
......
arch/arm/boot/dts/imx6qdl-aristainetos.dtsi 0 → 100644
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View file @ 1409f3fd
......@@ -121,9 +121,9 @@ reg_usb_otg_vbus: regulator@4 {
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
......@@ -489,7 +489,6 @@ &pwm4 {
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View file @ 1409f3fd
......@@ -124,9 +124,9 @@ reg_usb_otg_vbus: regulator@4 {
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
......@@ -533,7 +533,6 @@ &pwm4 {
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View file @ 1409f3fd
......@@ -114,9 +114,9 @@ reg_usb_otg_vbus: regulator@3 {
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
......@@ -555,12 +555,10 @@ &pwm4 {
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View file @ 1409f3fd
......@@ -381,7 +381,6 @@ &pwm4 {
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View file @ 1409f3fd
......@@ -301,6 +301,7 @@ &fec {
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
phy-supply = <&vdd_eth_io_reg>;
status = "disabled";
};
......
arch/arm/boot/dts/imx6qdl-rex.dtsi 0 → 100644
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
View file @ 1409f3fd
......@@ -381,7 +381,6 @@ &pwm4 {
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View file @ 1409f3fd
......@@ -340,6 +340,7 @@ pinctrl_ecspi1: ecspi1grp {
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
>;
};
......@@ -512,7 +513,6 @@ &pwm1 {
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-tx6.dtsi 0 → 100644
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "imx6qdl-wandboard.dtsi"
&iomuxc {
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
>;
};
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
status = "okay";
};
arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi 0 → 100644
View file @ 1409f3fd
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "imx6qdl-wandboard.dtsi"
&iomuxc {
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */
MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */
MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
>;
};
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
status = "okay";
};
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View file @ 1409f3fd
......@@ -91,22 +91,8 @@ codec: sgtl5000@0a {
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
......@@ -233,7 +219,6 @@ &spdif {
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
......@@ -269,13 +254,6 @@ &usdhc1 {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
......
arch/arm/boot/dts/imx6qdl.dtsi
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6sl-evk.dts
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6sl.dtsi
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6sx-pinfunc.h 0 → 100644
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6sx-sdb.dts 0 → 100644
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/imx6sx.dtsi 0 → 100644
View file @ 1409f3fd
This diff is collapsed.
arch/arm/boot/dts/vf610.dtsi
View file @ 1409f3fd
This diff is collapsed.
arch/arm/configs/imx_v4_v5_defconfig
View file @ 1409f3fd
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
......@@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_IMX27LITE=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_MXT_TD60=y
CONFIG_MACH_IMX27IPCAM=y
CONFIG_MACH_IMX27_DT=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
......@@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
......
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CONFIG_SYSVIPC=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_TASKSTATS=y
......
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