Commit 16b0e069 authored by Daniel Jurgens's avatar Daniel Jurgens Committed by Doug Ledford

IB/mlx5: Use cache line size to select CQE stride

When creating kernel CQs use 128B CQE stride if the
cache line size is 128B, 64B otherwise.  This prevents
multiple CQEs from residing in a 128B cache line,
which can cause retries when there are concurrent
read and writes in one cache line.

Tested with IPoIB on PPC64, saw ~5% throughput
improvement.

Fixes: e126ba97 ('mlx5: Add driver for Mellanox Connect-IB adapters')
Signed-off-by: default avatarDaniel Jurgens <danielj@mellanox.com>
Signed-off-by: default avatarMaor Gottlieb <maorg@mellanox.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent efd7f400
...@@ -932,8 +932,7 @@ struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, ...@@ -932,8 +932,7 @@ struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
if (err) if (err)
goto err_create; goto err_create;
} else { } else {
/* for now choose 64 bytes till we have a proper interface */ cqe_size = cache_line_size() == 128 ? 128 : 64;
cqe_size = 64;
err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
&index, &inlen); &index, &inlen);
if (err) if (err)
......
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