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Commit 16c4ea75 authored by Dong Aisheng's avatar Dong Aisheng Committed by Shawn Guo
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arm64: dts: imx8: switch to new lpcg clock binding 

switch to new lpcg clock binding
Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 26de33a1
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Showing with 59 additions and 63 deletions
arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
View file @ 16c4ea75
...@@ -20,13 +20,8 @@ dma_ipg_clk: clock-dma-ipg { ...@@ -20,13 +20,8 @@ dma_ipg_clk: clock-dma-ipg {
clock-output-names = "dma_ipg_clk"; clock-output-names = "dma_ipg_clk";
}; };
/* LPCG clocks */
adma_lpcg: clock-controller@59000000 {
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
};
dsp_lpcg: clock-controller@59580000 { dsp_lpcg: clock-controller@59580000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59580000 0x10000>; reg = <0x59580000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&dma_ipg_clk>, clocks = <&dma_ipg_clk>,
...@@ -41,6 +36,7 @@ dsp_lpcg: clock-controller@59580000 { ...@@ -41,6 +36,7 @@ dsp_lpcg: clock-controller@59580000 {
}; };
dsp_ram_lpcg: clock-controller@59590000 { dsp_ram_lpcg: clock-controller@59590000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59590000 0x10000>; reg = <0x59590000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&dma_ipg_clk>; clocks = <&dma_ipg_clk>;
...@@ -52,9 +48,9 @@ dsp_ram_lpcg: clock-controller@59590000 { ...@@ -52,9 +48,9 @@ dsp_ram_lpcg: clock-controller@59590000 {
adma_dsp: dsp@596e8000 { adma_dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp"; compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>; reg = <0x596e8000 0x88000>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; <&dsp_lpcg IMX_LPCG_CLK_7>;
clock-names = "ipg", "ocram", "core"; clock-names = "ipg", "ocram", "core";
power-domains = <&pd IMX_SC_R_MU_13A>, power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>, <&pd IMX_SC_R_MU_13B>,
...@@ -73,8 +69,8 @@ adma_dsp: dsp@596e8000 { ...@@ -73,8 +69,8 @@ adma_dsp: dsp@596e8000 {
adma_lpuart0: serial@5a060000 { adma_lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>; reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
<&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; <&uart0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud"; clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_0>; power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled"; status = "disabled";
...@@ -83,8 +79,8 @@ adma_lpuart0: serial@5a060000 { ...@@ -83,8 +79,8 @@ adma_lpuart0: serial@5a060000 {
adma_lpuart1: serial@5a070000 { adma_lpuart1: serial@5a070000 {
reg = <0x5a070000 0x1000>; reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
<&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; <&uart1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud"; clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_1>; power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled"; status = "disabled";
...@@ -93,8 +89,8 @@ adma_lpuart1: serial@5a070000 { ...@@ -93,8 +89,8 @@ adma_lpuart1: serial@5a070000 {
adma_lpuart2: serial@5a080000 { adma_lpuart2: serial@5a080000 {
reg = <0x5a080000 0x1000>; reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
<&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; <&uart2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud"; clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_2>; power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled"; status = "disabled";
...@@ -103,14 +99,15 @@ adma_lpuart2: serial@5a080000 { ...@@ -103,14 +99,15 @@ adma_lpuart2: serial@5a080000 {
adma_lpuart3: serial@5a090000 { adma_lpuart3: serial@5a090000 {
reg = <0x5a090000 0x1000>; reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
<&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; <&uart3_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud"; clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_3>; power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled"; status = "disabled";
}; };
uart0_lpcg: clock-controller@5a460000 { uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>; reg = <0x5a460000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
...@@ -122,6 +119,7 @@ uart0_lpcg: clock-controller@5a460000 { ...@@ -122,6 +119,7 @@ uart0_lpcg: clock-controller@5a460000 {
}; };
uart1_lpcg: clock-controller@5a470000 { uart1_lpcg: clock-controller@5a470000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a470000 0x10000>; reg = <0x5a470000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
...@@ -133,6 +131,7 @@ uart1_lpcg: clock-controller@5a470000 { ...@@ -133,6 +131,7 @@ uart1_lpcg: clock-controller@5a470000 {
}; };
uart2_lpcg: clock-controller@5a480000 { uart2_lpcg: clock-controller@5a480000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a480000 0x10000>; reg = <0x5a480000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
...@@ -144,6 +143,7 @@ uart2_lpcg: clock-controller@5a480000 { ...@@ -144,6 +143,7 @@ uart2_lpcg: clock-controller@5a480000 {
}; };
uart3_lpcg: clock-controller@5a490000 { uart3_lpcg: clock-controller@5a490000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a490000 0x10000>; reg = <0x5a490000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
...@@ -157,7 +157,7 @@ uart3_lpcg: clock-controller@5a490000 { ...@@ -157,7 +157,7 @@ uart3_lpcg: clock-controller@5a490000 {
adma_i2c0: i2c@5a800000 { adma_i2c0: i2c@5a800000 {
reg = <0x5a800000 0x4000>; reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
clock-names = "per"; clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>; assigned-clock-rates = <24000000>;
...@@ -168,7 +168,7 @@ adma_i2c0: i2c@5a800000 { ...@@ -168,7 +168,7 @@ adma_i2c0: i2c@5a800000 {
adma_i2c1: i2c@5a810000 { adma_i2c1: i2c@5a810000 {
reg = <0x5a810000 0x4000>; reg = <0x5a810000 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
clock-names = "per"; clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>; assigned-clock-rates = <24000000>;
...@@ -179,7 +179,7 @@ adma_i2c1: i2c@5a810000 { ...@@ -179,7 +179,7 @@ adma_i2c1: i2c@5a810000 {
adma_i2c2: i2c@5a820000 { adma_i2c2: i2c@5a820000 {
reg = <0x5a820000 0x4000>; reg = <0x5a820000 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
clock-names = "per"; clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>; assigned-clock-rates = <24000000>;
...@@ -190,7 +190,7 @@ adma_i2c2: i2c@5a820000 { ...@@ -190,7 +190,7 @@ adma_i2c2: i2c@5a820000 {
adma_i2c3: i2c@5a830000 { adma_i2c3: i2c@5a830000 {
reg = <0x5a830000 0x4000>; reg = <0x5a830000 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
clock-names = "per"; clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>; assigned-clock-rates = <24000000>;
...@@ -199,6 +199,7 @@ adma_i2c3: i2c@5a830000 { ...@@ -199,6 +199,7 @@ adma_i2c3: i2c@5a830000 {
}; };
i2c0_lpcg: clock-controller@5ac00000 { i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>; reg = <0x5ac00000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
...@@ -210,6 +211,7 @@ i2c0_lpcg: clock-controller@5ac00000 { ...@@ -210,6 +211,7 @@ i2c0_lpcg: clock-controller@5ac00000 {
}; };
i2c1_lpcg: clock-controller@5ac10000 { i2c1_lpcg: clock-controller@5ac10000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac10000 0x10000>; reg = <0x5ac10000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
...@@ -221,6 +223,7 @@ i2c1_lpcg: clock-controller@5ac10000 { ...@@ -221,6 +223,7 @@ i2c1_lpcg: clock-controller@5ac10000 {
}; };
i2c2_lpcg: clock-controller@5ac20000 { i2c2_lpcg: clock-controller@5ac20000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac20000 0x10000>; reg = <0x5ac20000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
...@@ -232,6 +235,7 @@ i2c2_lpcg: clock-controller@5ac20000 { ...@@ -232,6 +235,7 @@ i2c2_lpcg: clock-controller@5ac20000 {
}; };
i2c3_lpcg: clock-controller@5ac30000 { i2c3_lpcg: clock-controller@5ac30000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac30000 0x10000>; reg = <0x5ac30000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
......
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View file @ 16c4ea75
...@@ -37,10 +37,10 @@ conn_ipg_clk: clock-conn-ipg { ...@@ -37,10 +37,10 @@ conn_ipg_clk: clock-conn-ipg {
usdhc1: mmc@5b010000 { usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>; reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>, <&sdhc0_lpcg IMX_LPCG_CLK_5>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>; <&sdhc0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>; power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled"; status = "disabled";
}; };
...@@ -48,10 +48,10 @@ usdhc1: mmc@5b010000 { ...@@ -48,10 +48,10 @@ usdhc1: mmc@5b010000 {
usdhc2: mmc@5b020000 { usdhc2: mmc@5b020000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>; reg = <0x5b020000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>, <&sdhc1_lpcg IMX_LPCG_CLK_5>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>; <&sdhc1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_1>; power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>; fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>; fsl,tuning-step= <2>;
...@@ -61,10 +61,10 @@ usdhc2: mmc@5b020000 { ...@@ -61,10 +61,10 @@ usdhc2: mmc@5b020000 {
usdhc3: mmc@5b030000 { usdhc3: mmc@5b030000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>; reg = <0x5b030000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>, <&sdhc2_lpcg IMX_LPCG_CLK_5>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>; <&sdhc2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_2>; power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled"; status = "disabled";
}; };
...@@ -75,10 +75,10 @@ fec1: ethernet@5b040000 { ...@@ -75,10 +75,10 @@ fec1: ethernet@5b040000 {
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, <&enet0_lpcg IMX_LPCG_CLK_2>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, <&enet0_lpcg IMX_LPCG_CLK_1>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; <&enet0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>; fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>; fsl,num-rx-queues=<3>;
...@@ -92,10 +92,10 @@ fec2: ethernet@5b050000 { ...@@ -92,10 +92,10 @@ fec2: ethernet@5b050000 {
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, <&enet1_lpcg IMX_LPCG_CLK_2>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, <&enet1_lpcg IMX_LPCG_CLK_1>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; <&enet1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>; fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>; fsl,num-rx-queues=<3>;
...@@ -104,12 +104,8 @@ fec2: ethernet@5b050000 { ...@@ -104,12 +104,8 @@ fec2: ethernet@5b050000 {
}; };
/* LPCG clocks */ /* LPCG clocks */
conn_lpcg: clock-controller-legacy@5b200000 {
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
sdhc0_lpcg: clock-controller@5b200000 { sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b200000 0x10000>; reg = <0x5b200000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
...@@ -123,6 +119,7 @@ sdhc0_lpcg: clock-controller@5b200000 { ...@@ -123,6 +119,7 @@ sdhc0_lpcg: clock-controller@5b200000 {
}; };
sdhc1_lpcg: clock-controller@5b210000 { sdhc1_lpcg: clock-controller@5b210000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b210000 0x10000>; reg = <0x5b210000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
...@@ -136,6 +133,7 @@ sdhc1_lpcg: clock-controller@5b210000 { ...@@ -136,6 +133,7 @@ sdhc1_lpcg: clock-controller@5b210000 {
}; };
sdhc2_lpcg: clock-controller@5b220000 { sdhc2_lpcg: clock-controller@5b220000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b220000 0x10000>; reg = <0x5b220000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
...@@ -149,6 +147,7 @@ sdhc2_lpcg: clock-controller@5b220000 { ...@@ -149,6 +147,7 @@ sdhc2_lpcg: clock-controller@5b220000 {
}; };
enet0_lpcg: clock-controller@5b230000 { enet0_lpcg: clock-controller@5b230000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b230000 0x10000>; reg = <0x5b230000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
...@@ -166,6 +165,7 @@ enet0_lpcg: clock-controller@5b230000 { ...@@ -166,6 +165,7 @@ enet0_lpcg: clock-controller@5b230000 {
}; };
enet1_lpcg: clock-controller@5b240000 { enet1_lpcg: clock-controller@5b240000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b240000 0x10000>; reg = <0x5b240000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
......
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
View file @ 16c4ea75
...@@ -149,12 +149,8 @@ lsio_mu13: mailbox@5d280000 { ...@@ -149,12 +149,8 @@ lsio_mu13: mailbox@5d280000 {
}; };
/* LPCG clocks */ /* LPCG clocks */
lsio_lpcg: clock-controller-legacy@5d400000 {
reg = <0x5d400000 0x400000>;
#clock-cells = <1>;
};
pwm0_lpcg: clock-controller@5d400000 { pwm0_lpcg: clock-controller@5d400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d400000 0x10000>; reg = <0x5d400000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
...@@ -174,6 +170,7 @@ pwm0_lpcg: clock-controller@5d400000 { ...@@ -174,6 +170,7 @@ pwm0_lpcg: clock-controller@5d400000 {
}; };
pwm1_lpcg: clock-controller@5d410000 { pwm1_lpcg: clock-controller@5d410000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d410000 0x10000>; reg = <0x5d410000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
...@@ -193,6 +190,7 @@ pwm1_lpcg: clock-controller@5d410000 { ...@@ -193,6 +190,7 @@ pwm1_lpcg: clock-controller@5d410000 {
}; };
pwm2_lpcg: clock-controller@5d420000 { pwm2_lpcg: clock-controller@5d420000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d420000 0x10000>; reg = <0x5d420000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
...@@ -212,6 +210,7 @@ pwm2_lpcg: clock-controller@5d420000 { ...@@ -212,6 +210,7 @@ pwm2_lpcg: clock-controller@5d420000 {
}; };
pwm3_lpcg: clock-controller@5d430000 { pwm3_lpcg: clock-controller@5d430000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d430000 0x10000>; reg = <0x5d430000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
...@@ -231,6 +230,7 @@ pwm3_lpcg: clock-controller@5d430000 { ...@@ -231,6 +230,7 @@ pwm3_lpcg: clock-controller@5d430000 {
}; };
pwm4_lpcg: clock-controller@5d440000 { pwm4_lpcg: clock-controller@5d440000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d440000 0x10000>; reg = <0x5d440000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
...@@ -250,6 +250,7 @@ pwm4_lpcg: clock-controller@5d440000 { ...@@ -250,6 +250,7 @@ pwm4_lpcg: clock-controller@5d440000 {
}; };
pwm5_lpcg: clock-controller@5d450000 { pwm5_lpcg: clock-controller@5d450000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d450000 0x10000>; reg = <0x5d450000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
...@@ -269,6 +270,7 @@ pwm5_lpcg: clock-controller@5d450000 { ...@@ -269,6 +270,7 @@ pwm5_lpcg: clock-controller@5d450000 {
}; };
pwm6_lpcg: clock-controller@5d460000 { pwm6_lpcg: clock-controller@5d460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d460000 0x10000>; reg = <0x5d460000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
...@@ -288,6 +290,7 @@ pwm6_lpcg: clock-controller@5d460000 { ...@@ -288,6 +290,7 @@ pwm6_lpcg: clock-controller@5d460000 {
}; };
pwm7_lpcg: clock-controller@5d470000 { pwm7_lpcg: clock-controller@5d470000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d470000 0x10000>; reg = <0x5d470000 0x10000>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
......
arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
View file @ 16c4ea75
...@@ -4,10 +4,6 @@ ...@@ -4,10 +4,6 @@
* Dong Aisheng <aisheng.dong@nxp.com> * Dong Aisheng <aisheng.dong@nxp.com>
*/ */
&adma_lpcg {
compatible = "fsl,imx8qxp-lpcg-adma";
};
&adma_lpuart0 { &adma_lpuart0 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
}; };
......
arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
View file @ 16c4ea75
...@@ -4,10 +4,6 @@ ...@@ -4,10 +4,6 @@
* Dong Aisheng <aisheng.dong@nxp.com> * Dong Aisheng <aisheng.dong@nxp.com>
*/ */
&conn_lpcg {
compatible = "fsl,imx8qxp-lpcg-conn";
};
&usdhc1 { &usdhc1 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
}; };
......
arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
View file @ 16c4ea75
...@@ -59,7 +59,3 @@ &lsio_mu4 { ...@@ -59,7 +59,3 @@ &lsio_mu4 {
&lsio_mu13 { &lsio_mu13 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
}; };
&lsio_lpcg {
compatible = "fsl,imx8qxp-lpcg-lsio";
};
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View file @ 16c4ea75
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
*/ */
#include <dt-bindings/clock/imx8-clock.h> #include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h> #include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
......
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