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Commit 16fa9311 authored by Komal Bajaj's avatar Komal Bajaj Committed by Bjorn Andersson
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soc: qcom: llcc: Refactor llcc driver to support multiple configuration 

Refactor driver to support multiple configuration for llcc on a target.
Signed-off-by: default avatarKomal Bajaj <quic_kbajaj@quicinc.com>
Fixes: ee13b500 ("qcom: llcc/edac: Fix the base address used for  accessing LLCC banks")
Reviewed-by: default avatarMukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830105654.28057-3-quic_kbajaj@quicinc.comSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 8e2506d0
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Showing with 181 additions and 86 deletions
drivers/soc/qcom/llcc-qcom.c
View file @ 16fa9311
......@@ -126,6 +126,11 @@ struct qcom_llcc_config {
bool no_edac;
};
struct qcom_sct_config {
const struct qcom_llcc_config *llcc_config;
int num_config;
};
enum llcc_reg_offset {
LLCC_COMMON_HW_INFO,
LLCC_COMMON_STATUS0,
......@@ -422,101 +427,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
[LLCC_COMMON_STATUS0] = 0x0003400c,
};
static const struct qcom_llcc_config sc7180_cfg = {
.sct_data = sc7180_data,
.size = ARRAY_SIZE(sc7180_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_llcc_config sc7180_cfg[] = {
{
.sct_data = sc7180_data,
.size = ARRAY_SIZE(sc7180_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sc7280_cfg[] = {
{
.sct_data = sc7280_data,
.size = ARRAY_SIZE(sc7280_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sc8180x_cfg[] = {
{
.sct_data = sc8180x_data,
.size = ARRAY_SIZE(sc8180x_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sc8280xp_cfg[] = {
{
.sct_data = sc8280xp_data,
.size = ARRAY_SIZE(sc8280xp_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sdm845_cfg[] = {
{
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
.need_llcc_cfg = false,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
.no_edac = true,
},
};
static const struct qcom_llcc_config sm6350_cfg[] = {
{
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sm7150_cfg[] = {
{
.sct_data = sm7150_data,
.size = ARRAY_SIZE(sm7150_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sm8150_cfg[] = {
{
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sm8250_cfg[] = {
{
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sm8350_cfg[] = {
{
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sc7280_cfg = {
.sct_data = sc7280_data,
.size = ARRAY_SIZE(sc7280_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_llcc_config sm8450_cfg[] = {
{
.sct_data = sm8450_data,
.size = ARRAY_SIZE(sm8450_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sm8550_cfg[] = {
{
.sct_data = sm8550_data,
.size = ARRAY_SIZE(sm8550_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
};
static const struct qcom_sct_config sc7180_cfgs = {
.llcc_config = sc7180_cfg,
.num_config = ARRAY_SIZE(sc7180_cfg),
};
static const struct qcom_sct_config sc7280_cfgs = {
.llcc_config = sc7280_cfg,
.num_config = ARRAY_SIZE(sc7280_cfg),
};
static const struct qcom_llcc_config sc8180x_cfg = {
.sct_data = sc8180x_data,
.size = ARRAY_SIZE(sc8180x_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_sct_config sc8180x_cfgs = {
.llcc_config = sc8180x_cfg,
.num_config = ARRAY_SIZE(sc8180x_cfg),
};
static const struct qcom_llcc_config sc8280xp_cfg = {
.sct_data = sc8280xp_data,
.size = ARRAY_SIZE(sc8280xp_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_sct_config sc8280xp_cfgs = {
.llcc_config = sc8280xp_cfg,
.num_config = ARRAY_SIZE(sc8280xp_cfg),
};
static const struct qcom_llcc_config sdm845_cfg = {
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
.need_llcc_cfg = false,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
.no_edac = true,
static const struct qcom_sct_config sdm845_cfgs = {
.llcc_config = sdm845_cfg,
.num_config = ARRAY_SIZE(sdm845_cfg),
};
static const struct qcom_llcc_config sm6350_cfg = {
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_sct_config sm6350_cfgs = {
.llcc_config = sm6350_cfg,
.num_config = ARRAY_SIZE(sm6350_cfg),
};
static const struct qcom_llcc_config sm7150_cfg = {
.sct_data = sm7150_data,
.size = ARRAY_SIZE(sm7150_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_sct_config sm7150_cfgs = {
.llcc_config = sm7150_cfg,
.num_config = ARRAY_SIZE(sm7150_cfg),
};
static const struct qcom_llcc_config sm8150_cfg = {
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_sct_config sm8150_cfgs = {
.llcc_config = sm8150_cfg,
.num_config = ARRAY_SIZE(sm8150_cfg),
};
static const struct qcom_llcc_config sm8250_cfg = {
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_sct_config sm8250_cfgs = {
.llcc_config = sm8250_cfg,
.num_config = ARRAY_SIZE(sm8250_cfg),
};
static const struct qcom_llcc_config sm8350_cfg = {
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
static const struct qcom_sct_config sm8350_cfgs = {
.llcc_config = sm8350_cfg,
.num_config = ARRAY_SIZE(sm8350_cfg),
};
static const struct qcom_llcc_config sm8450_cfg = {
.sct_data = sm8450_data,
.size = ARRAY_SIZE(sm8450_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
static const struct qcom_sct_config sm8450_cfgs = {
.llcc_config = sm8450_cfg,
.num_config = ARRAY_SIZE(sm8450_cfg),
};
static const struct qcom_llcc_config sm8550_cfg = {
.sct_data = sm8550_data,
.size = ARRAY_SIZE(sm8550_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
static const struct qcom_sct_config sm8550_cfgs = {
.llcc_config = sm8550_cfg,
.num_config = ARRAY_SIZE(sm8550_cfg),
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
......@@ -938,6 +1027,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
int ret, i;
struct platform_device *llcc_edac;
const struct qcom_sct_config *cfgs;
const struct qcom_llcc_config *cfg;
const struct llcc_slice_config *llcc_cfg;
u32 sz;
......@@ -957,7 +1047,12 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
}
cfg = of_device_get_match_data(&pdev->dev);
cfgs = of_device_get_match_data(&pdev->dev);
if (!cfgs) {
ret = -EINVAL;
goto err;
}
cfg = &cfgs->llcc_config[0];
ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
if (ret)
......@@ -1050,18 +1145,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
......
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