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Commit 175159c5 authored by Larry Finger's avatar Larry Finger
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staging: rtl8192e: Remove code dependent on RTL8190P 

The vendor code can conditionally generate drivers for a number of
devices. Remove any code that depends on RTL8190P being set.
Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
parent d6f2deb3
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Showing with 0 additions and 755 deletions
drivers/staging/rtl8192e/r8190P_rtl8256.c
View file @ 175159c5
......@@ -193,40 +193,6 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
{
u32 TxAGC=0;
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef RTL8190P
u8 byte0, byte1;
TxAGC |= ((powerlevel<<8)|powerlevel);
TxAGC += priv->CCKTxPowerLevelOriginalOffset;
if (priv->bDynamicTxLowPower == true
/*pMgntInfo->bScanInProgress == true*/ )
{
if (priv->CustomerID == RT_CID_819x_Netcore)
TxAGC = 0x2222;
else
TxAGC += ((priv->CckPwEnl<<8)|priv->CckPwEnl);
}
byte0 = (u8)(TxAGC & 0xff);
byte1 = (u8)((TxAGC & 0xff00)>>8);
if (byte0 > 0x24)
byte0 = 0x24;
if (byte1 > 0x24)
byte1 = 0x24;
if (priv->rf_type == RF_2T4R)
{
if (priv->RF_C_TxPwDiff > 0)
{
if ( (byte0 + (u8)priv->RF_C_TxPwDiff) > 0x24)
byte0 = 0x24 - priv->RF_C_TxPwDiff;
if ( (byte1 + (u8)priv->RF_C_TxPwDiff) > 0x24)
byte1 = 0x24 - priv->RF_C_TxPwDiff;
}
}
TxAGC = (byte1<<8) |byte0;
write_nic_dword(dev, CCK_TXAGC, TxAGC);
#else
#ifdef RTL8192E
TxAGC = powerlevel;
......@@ -241,77 +207,12 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
TxAGC = 0x24;
rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
#endif
#endif
}
void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
{
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef RTL8190P
u32 TxAGC1=0, TxAGC2=0, TxAGC2_tmp = 0;
u8 i, byteVal1[4], byteVal2[4], byteVal3[4];
if (priv->bDynamicTxHighPower == true)
{
TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
TxAGC2_tmp = TxAGC1;
TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
TxAGC2 =0x03030303;
TxAGC2_tmp += priv->MCSTxPowerLevelOriginalOffset[1];
}
else
{
TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
TxAGC2 = TxAGC1;
TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
TxAGC2 += priv->MCSTxPowerLevelOriginalOffset[1];
TxAGC2_tmp = TxAGC2;
}
for (i=0; i<4; i++)
{
byteVal1[i] = (u8)( (TxAGC1 & (0xff<<(i*8))) >>(i*8) );
if (byteVal1[i] > 0x24)
byteVal1[i] = 0x24;
byteVal2[i] = (u8)( (TxAGC2 & (0xff<<(i*8))) >>(i*8) );
if (byteVal2[i] > 0x24)
byteVal2[i] = 0x24;
byteVal3[i] = (u8)( (TxAGC2_tmp & (0xff<<(i*8))) >>(i*8) );
if (byteVal3[i] > 0x24)
byteVal3[i] = 0x24;
}
if (priv->rf_type == RF_2T4R)
{
if (priv->RF_C_TxPwDiff > 0)
{
for (i=0; i<4; i++)
{
if ( (byteVal1[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
byteVal1[i] = 0x24 - priv->RF_C_TxPwDiff;
if ( (byteVal2[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
byteVal2[i] = 0x24 - priv->RF_C_TxPwDiff;
if ( (byteVal3[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
byteVal3[i] = 0x24 - priv->RF_C_TxPwDiff;
}
}
}
TxAGC1 = (byteVal1[3]<<24) | (byteVal1[2]<<16) |(byteVal1[1]<<8) |byteVal1[0];
TxAGC2 = (byteVal2[3]<<24) | (byteVal2[2]<<16) |(byteVal2[1]<<8) |byteVal2[0];
TxAGC2_tmp = (byteVal3[3]<<24) | (byteVal3[2]<<16) |(byteVal3[1]<<8) |byteVal3[0];
priv->Pwr_Track = TxAGC2_tmp;
write_nic_dword(dev, MCS_TXAGC, TxAGC1);
write_nic_dword(dev, MCS_TXAGC+4, TxAGC2);
#else
#ifdef RTL8192E
u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
u8 index = 0;
......@@ -356,7 +257,6 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
}
#endif
#endif
return;
}
......
drivers/staging/rtl8192e/r8190P_rtl8256.h
View file @ 175159c5
......@@ -20,11 +20,7 @@
#ifndef RTL8225H
#define RTL8225H
#ifdef RTL8190P
#define RTL819X_TOTAL_RF_PATH 4
#else
#define RTL819X_TOTAL_RF_PATH 2
#endif
extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth);
extern bool PHY_RF8256_Config(struct net_device* dev);
extern bool phy_RF8256_Config_ParaFile(struct net_device* dev);
......
drivers/staging/rtl8192e/r8192E_cmdpkt.c
View file @ 175159c5
......@@ -16,7 +16,6 @@
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#if (defined(RTL8192E) || defined(RTL8190P))
#include "rtl_core.h"
#include "r8192E_hw.h"
......@@ -453,6 +452,3 @@ cmpk_message_handle_rx(
RT_TRACE(COMP_CMDPKT, "<----cmpk_message_handle_rx()\n");
}
#endif
drivers/staging/rtl8192e/r8192E_dev.c
View file @ 175159c5
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_firmware.c
View file @ 175159c5
......@@ -216,12 +216,6 @@ inline static bool firmware_check_ready(struct net_device *dev, u8 load_fw_statu
switch (load_fw_status) {
case FW_INIT_STEP0_BOOT:
pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE;
#ifdef RTL8190P
rt_status = fwSendNullPacket(dev, RTL8190_CPU_START_OFFSET);
if (!rt_status) {
RT_TRACE(COMP_INIT, "fwSendNullPacket() fail ! \n");
}
#endif
break;
case FW_INIT_STEP1_MAIN:
......@@ -262,15 +256,6 @@ bool init_firmware(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev);
bool rt_status = true;
#ifdef RTL8190P
u8 *firmware_img_buf[3] = { &Rtl8190PciFwBootArray[0],
&Rtl8190PciFwMainArray[0],
&Rtl8190PciFwDataArray[0]};
u32 firmware_img_len[3] = { sizeof(Rtl8190PciFwBootArray),
sizeof(Rtl8190PciFwMainArray),
sizeof(Rtl8190PciFwDataArray)};
#else
u8 *firmware_img_buf[3] = { &Rtl8192PciEFwBootArray[0],
&Rtl8192PciEFwMainArray[0],
&Rtl8192PciEFwDataArray[0]};
......@@ -278,7 +263,6 @@ bool init_firmware(struct net_device *dev)
u32 firmware_img_len[3] = { sizeof(Rtl8192PciEFwBootArray),
sizeof(Rtl8192PciEFwMainArray),
sizeof(Rtl8192PciEFwDataArray)};
#endif
u32 file_length = 0;
u8 *mapped_file = NULL;
u8 init_step = 0;
......
drivers/staging/rtl8192e/r8192E_hw.h
View file @ 175159c5
......@@ -70,19 +70,6 @@ typedef enum _BaseBand_Config_Type {
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_ICVersion_ChannelPlan 0x7C
#define EEPROM_Customer_ID 0x7B
#ifdef RTL8190P
#define EEPROM_RFInd_PowerDiff 0x14
#define EEPROM_ThermalMeter 0x15
#define EEPROM_TxPwDiff_CrystalCap 0x16
#define EEPROM_TxPwIndex_CCK 0x18
#define EEPROM_TxPwIndex_OFDM_24G 0x26
#define EEPROM_TxPwIndex_OFDM_5G 0x34
#define EEPROM_C56_CrystalCap 0x17
#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80
#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81
#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc
#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9
#else
#ifdef RTL8192E
#define EEPROM_RFInd_PowerDiff 0x28
#define EEPROM_ThermalMeter 0x29
......@@ -90,7 +77,6 @@ typedef enum _BaseBand_Config_Type {
#define EEPROM_TxPwIndex_CCK 0x2C
#define EEPROM_TxPwIndex_OFDM_24G 0x3A
#endif
#endif
#define EEPROM_Default_TxPowerLevel 0x10
#define EEPROM_IC_VER 0x7d
#define EEPROM_CRC 0x7e
......
drivers/staging/rtl8192e/r8192E_phy.c
View file @ 175159c5
......@@ -16,8 +16,6 @@
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#if (defined(RTL8192E) || defined(RTL8190P))
#include "rtl_core.h"
#include "r8192E_hw.h"
......@@ -29,10 +27,6 @@
#include "dot11d.h"
#endif
#ifdef RTL8190P
#include "r8190P_hwimg.h"
#endif
#ifdef RTL8192E
#include "r8192E_hwimg.h"
#endif
......@@ -73,19 +67,6 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
{
u8 ret = 1;
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef RTL8190P
if (priv->rf_type == RF_2T4R)
{
ret= 1;
}
else if (priv->rf_type == RF_1T2R)
{
if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
ret = 0;
else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
ret = 1;
}
#else
#ifdef RTL8192E
if (priv->rf_type == RF_2T4R)
ret = 0;
......@@ -97,7 +78,6 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
ret = 0;
}
#endif
#endif
return ret;
}
void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
......@@ -135,13 +115,9 @@ u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath,
if (priv->rf_chip == RF_8256)
{
#ifdef RTL8190P
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
#else
#ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
#endif
#endif
if (Offset >= 31)
{
priv->RfReg0Value[eRFPath] |= 0x140;
......@@ -184,20 +160,9 @@ u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath,
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
#ifdef RTL8190P
if (priv->rf_type == RF_2T4R)
{
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
}
else if (priv->rf_type == RF_1T2R)
{
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);
}
#else
#ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
#endif
#endif
}
......@@ -215,13 +180,9 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath
if (priv->rf_chip == RF_8256)
{
#ifdef RTL8190P
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
#else
#ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
#endif
#endif
if (Offset >= 31)
{
......@@ -264,20 +225,9 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
}
#ifdef RTL8190P
if (priv->rf_type == RF_2T4R)
{
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
}
else if (priv->rf_type == RF_1T2R)
{
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);
}
#else
#ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
#endif
#endif
}
return;
......@@ -705,17 +655,10 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev)
(bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
#ifdef RTL8190P
dwRegValue = priv->CrystalCap & 0x3;
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
dwRegValue = ((priv->CrystalCap & 0xc)>>2);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
#else
#ifdef RTL8192E
dwRegValue = priv->CrystalCap;
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
#endif
#endif
}
......@@ -732,14 +675,6 @@ bool rtl8192_BBConfig(struct net_device* dev)
void rtl8192_phy_getTxPower(struct net_device* dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef RTL8190P
priv->MCSTxPowerLevelOriginalOffset[0] =
read_nic_dword(dev, MCS_TXAGC);
priv->MCSTxPowerLevelOriginalOffset[1] =
read_nic_dword(dev, (MCS_TXAGC+4));
priv->CCKTxPowerLevelOriginalOffset =
read_nic_dword(dev, CCK_TXAGC);
#else
#ifdef RTL8192E
priv->MCSTxPowerLevelOriginalOffset[0] =
read_nic_dword(dev, rTxAGC_Rate18_06);
......@@ -754,7 +689,6 @@ void rtl8192_phy_getTxPower(struct net_device* dev)
priv->MCSTxPowerLevelOriginalOffset[5] =
read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
#endif
#endif
priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
......@@ -1246,7 +1180,6 @@ static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
}
}
#ifndef RTL8190P
static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
......@@ -1272,7 +1205,6 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
}
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
}
#endif
static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
{
......@@ -1280,14 +1212,10 @@ static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev);
#endif
#ifdef RTL8190P
CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
#else
if (priv->IC_Cut >= IC_VersionCut_D)
CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
else
CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
#endif
}
void rtl8192_SetBWModeWorkItem(struct net_device *dev)
......@@ -1343,14 +1271,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
else
CCK_Tx_Power_Track_BW_Switch(dev);
#ifdef RTL8190P
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44);
#else
#ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
#endif
#endif
break;
case HT_CHANNEL_WIDTH_20_40:
......@@ -1370,23 +1293,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
#ifdef RTL8190P
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42);
if (priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
{
rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
}else if (priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
{
rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
}
#else
#ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
#endif
#endif
break;
default:
RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
......@@ -1518,26 +1427,6 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation)
}
}
#if defined RTL8190P
extern void
PHY_SetRtl8190pRfOff(struct net_device* dev )
{
struct r8192_priv *priv = rtllib_priv(dev);
if (priv->rf_type == RF_2T4R)
{
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
}
rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0x0);
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0x0);
}
#endif
#if defined RTL8192E
extern void
PHY_SetRtl8192eRfOff(struct net_device* dev )
......@@ -1582,37 +1471,6 @@ SetRFPowerState8190(
{
case eRfOn:
RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n");
#ifdef RTL8190P
if (priv->rf_type == RF_2T4R)
{
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);
rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf);
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf);
}
else if (priv->rf_type == RF_1T2R)
{
rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3);
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3);
}
else if (priv->rf_type == RF_1T1R)
{
rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1);
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1);
}
#elif defined RTL8192E
if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{
bool rtstatus = true;
......@@ -1647,7 +1505,6 @@ SetRFPowerState8190(
}
#endif
break;
case eRfSleep:
......@@ -1687,15 +1544,9 @@ SetRFPowerState8190(
}
}
#ifdef RTL8190P
{
PHY_SetRtl8190pRfOff(dev);
}
#elif defined RTL8192E
{
PHY_SetRtl8192eRfOff(dev);
}
#endif
}
break;
......@@ -1733,11 +1584,6 @@ SetRFPowerState8190(
}
}
#if defined RTL8190P
{
PHY_SetRtl8190pRfOff(dev);
}
#elif defined RTL8192E
{
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{
......@@ -1760,12 +1606,6 @@ SetRFPowerState8190(
}
#endif
}
#else
else
{
RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n"));
}
#endif
break;
......@@ -1882,5 +1722,3 @@ PHY_ScanOperationBackup8192(
}
}
#endif
drivers/staging/rtl8192e/r8192E_phy.h
View file @ 175159c5
......@@ -25,28 +25,6 @@
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
#ifdef RTL8190P
#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPci
#define MACPHY_ArrayLength MACPHY_ArrayLengthPci
#define RadioA_ArrayLength RadioA_ArrayLengthPci
#define RadioB_ArrayLength RadioB_ArrayLengthPci
#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPci
#define RadioC_ArrayLength RadioC_ArrayLengthPci
#define RadioD_ArrayLength RadioD_ArrayLengthPci
#define PHY_REGArrayLength PHY_REGArrayLengthPci
#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPci
#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG
#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array
#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array
#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array
#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array
#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array
#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array
#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray
#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray
#endif
#ifdef RTL8192E
#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
......@@ -142,11 +120,6 @@ extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
#if defined RTL8190P
extern void
PHY_SetRtl8190pRfOff(struct net_device* dev );
#endif
#if defined RTL8192E
extern void
PHY_SetRtl8192eRfOff(struct net_device* dev );
......
drivers/staging/rtl8192e/rtl819x_HTProc.c
View file @ 175159c5
......@@ -476,14 +476,10 @@ u8 HTIOTActIsMgntUseCCK6M(struct rtllib_device* ieee,struct rtllib_network *netw
u8 retValue = 0;
#if (defined RTL8192U || defined RTL8192E || defined RTL8190P)
{
if (ieee->pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
{
retValue = 1;
}
}
#endif
return retValue;
}
......@@ -563,12 +559,10 @@ HTIOTActIsForcedAMSDU8K(struct rtllib_device *ieee, struct rtllib_network *netwo
u8 HTIOTActIsCCDFsync(struct rtllib_device *ieee)
{
u8 retValue = 0;
#if (defined RTL8190P || defined RTL8192U || defined RTL8192SU)
if (ieee->pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
{
retValue = 1;
}
#endif
return retValue;
}
......@@ -1149,11 +1143,7 @@ void HTOnAssocRsp(struct rtllib_device *ieee)
ieee->SetHwRegHandler(ieee->dev, HW_VAR_AMPDU_MIN_SPACE, &pHTInfo->CurrentMPDUDensity);
}
#endif
#ifndef RTL8190P
if (pHTInfo->IOTAction & HT_IOT_ACT_TX_USE_AMSDU_8K)
#else
if ( 0 )
#endif
{
pHTInfo->bCurrentAMPDUEnable = false;
pHTInfo->ForcedAMSDUMode = HT_AGG_FORCE_ENABLE;
......@@ -1294,17 +1284,9 @@ void HTResetSelfAndSavePeerSetting(struct rtllib_device* ieee, struct rtllib_net
if (bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO;
#if defined(RTL8190P) || defined(RTL8192E) || defined(RTL8192U)
bIOTAction = HTIOTActIsMgntUseCCK6M(ieee,pNetwork);
if (bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_MGNT_USE_CCK_6M;
#elif defined(RTL8192SE) || defined(RTL8192SU) || defined RTL8192CE
bIOTAction = HTIOTActWAIOTBroadcom(ieee);
if (bIOTAction)
{
pHTInfo->IOTAction |= HT_IOT_ACT_WA_IOT_Broadcom;
}
#endif
bIOTAction = HTIOTActIsCCDFsync(ieee);
if (bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_CDD_FSYNC;
......
drivers/staging/rtl8192e/rtl_core.c
View file @ 175159c5
......@@ -626,20 +626,12 @@ void rtl8192_update_cap(struct net_device* dev, u16 cap)
}
}
#ifdef RTL8192CE
if ( net->mode & IEEE_G)
#elif defined RTL8192SE || defined RTL8192E || defined RTL8190P
if (net->mode & (IEEE_G|IEEE_N_24G))
#endif
{
u8 slot_time_val;
u8 CurSlotTime = priv->slot_time;
#ifdef RTL8192CE
if ( (cap & WLAN_CAPABILITY_SHORT_SLOT_TIME) && (!(priv->rtllib->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)))
#elif defined RTL8192SE || defined RTL8192E || defined RTL8190P
if ((cap & WLAN_CAPABILITY_SHORT_SLOT_TIME) && (!priv->rtllib->pHTInfo->bCurrentRT2RTLongSlotTime))
#endif
{
if (CurSlotTime != SHORT_SLOT_TIME)
{
......@@ -1281,7 +1273,6 @@ static void rtl8192_init_priv_constant(struct net_device* dev)
priv->RegSupportPciASPM = 2;
#elif defined RTL8190P
#endif
}
......@@ -1883,9 +1874,6 @@ void rtl819x_ifsilentreset(struct net_device *dev)
dm_backup_dynamic_mechanism_state(dev);
#endif
#ifdef RTL8190P
priv->ops->stop_adapter(dev, true);
#endif
up(&priv->wx_sem);
RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__func__);
......@@ -2608,56 +2596,6 @@ rtl819x_process_cck_rxpathsel(
struct rtllib_rx_stats * pprevious_stats
)
{
#ifdef RTL8190P
char last_cck_adc_pwdb[4]={0,0,0,0};
u8 i;
if (priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable)
{
if (pprevious_stats->bIsCCK &&
(pprevious_stats->bPacketToSelf ||pprevious_stats->bPacketBeacon))
{
if (priv->stats.cck_adc_pwdb.TotalNum++ >= PHY_RSSI_SLID_WIN_MAX)
{
priv->stats.cck_adc_pwdb.TotalNum = PHY_RSSI_SLID_WIN_MAX;
for (i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
{
last_cck_adc_pwdb[i] = priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index];
priv->stats.cck_adc_pwdb.TotalVal[i] -= last_cck_adc_pwdb[i];
}
}
for (i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
{
priv->stats.cck_adc_pwdb.TotalVal[i] += pprevious_stats->cck_adc_pwdb[i];
priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index] = pprevious_stats->cck_adc_pwdb[i];
}
priv->stats.cck_adc_pwdb.index++;
if (priv->stats.cck_adc_pwdb.index >= PHY_RSSI_SLID_WIN_MAX)
priv->stats.cck_adc_pwdb.index = 0;
for (i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
{
DM_RxPathSelTable.cck_pwdb_sta[i] = priv->stats.cck_adc_pwdb.TotalVal[i]/priv->stats.cck_adc_pwdb.TotalNum;
}
for (i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
{
if (pprevious_stats->cck_adc_pwdb[i] > (char)priv->undecorated_smoothed_cck_adc_pwdb[i])
{
priv->undecorated_smoothed_cck_adc_pwdb[i] =
( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
(pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
priv->undecorated_smoothed_cck_adc_pwdb[i] = priv->undecorated_smoothed_cck_adc_pwdb[i] + 1;
}
else
{
priv->undecorated_smoothed_cck_adc_pwdb[i] =
( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
(pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
}
}
}
}
#endif
}
......
drivers/staging/rtl8192e/rtl_dm.c
View file @ 175159c5
This diff is collapsed.
drivers/staging/rtl8192e/rtl_dm.h
View file @ 175159c5
......@@ -40,11 +40,7 @@
#define DM_DIG_BACKOFF 12
#ifdef RTL8192SE
#define DM_DIG_MAX 0x3e
#elif defined RTL8190P || defined RTL8192E
#define DM_DIG_MAX 0x36
#endif
#define DM_DIG_MIN 0x1c
#define DM_DIG_MIN_Netcore 0x12
......@@ -59,11 +55,7 @@
#define RateAdaptiveTH_Low_40M 10
#define VeryLowRSSI 15
#ifdef RTL8192SE
#define CTSToSelfTHVal 30
#elif defined RTL8190P || defined RTL8192E
#define CTSToSelfTHVal 35
#endif
#define WAIotTHVal 25
......
drivers/staging/rtl8192e/rtllib.h
View file @ 175159c5
......@@ -118,7 +118,6 @@ static inline void *netdev_priv_rsl(struct net_device *dev)
/* added for rtl819x tx procedure */
#define MAX_QUEUE_SIZE 0x10
#if defined(RTL8192SU) || defined(RTL8190P) ||defined(RTL8192U) ||defined(RTL8192E)
#define BK_QUEUE 0
#define BE_QUEUE 1
#define VI_QUEUE 2
......@@ -128,18 +127,6 @@ static inline void *netdev_priv_rsl(struct net_device *dev)
#define MGNT_QUEUE 6
#define HIGH_QUEUE 7
#define BEACON_QUEUE 8
#elif defined(RTL8192SE)
#define BK_QUEUE 0
#define BE_QUEUE 1
#define VI_QUEUE 2
#define VO_QUEUE 3
#define BEACON_QUEUE 4
#define TXCMD_QUEUE 5
#define MGNT_QUEUE 6
#define HIGH_QUEUE 7
#define HCCA_QUEUE 8
#endif
#define LOW_QUEUE BE_QUEUE
#define NORMAL_QUEUE MGNT_QUEUE
......
drivers/staging/rtl8192e/rtllib_softmac.c
View file @ 175159c5
......@@ -4051,9 +4051,7 @@ rtllib_MgntDisconnect(
{
if (rtllib->ps != RTLLIB_PS_DISABLED)
{
#ifndef RTL8190P
rtllib->sta_wake_up(rtllib->dev);
#endif
}
#ifdef TO_DO
......
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