perf vendor events: Add bonnell counter information

Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-4-irogers@google.com

tools/perf/pmu-events/arch/x86/bonnell/counter.json

+[
+    {
+        "Unit": "core",
+        "CountersNumFixed": "4",
+        "CountersNumGeneric": "2"
+    }
+]
\ No newline at end of file

tools/perf/pmu-events/arch/x86/bonnell/floating-point.json

 [
     {
         "BriefDescription": "Floating point assists for retired operations.",
+        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "FP_ASSIST.AR",
         "SampleAfterValue": "10000",
@@ -8,6 +9,7 @@
     },
     {
         "BriefDescription": "Floating point assists.",
+        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "FP_ASSIST.S",
         "SampleAfterValue": "10000",
@@ -15,12 +17,14 @@
     },
     {
         "BriefDescription": "SIMD assists invoked.",
+        "Counter": "0,1",
         "EventCode": "0xCD",
         "EventName": "SIMD_ASSIST",
         "SampleAfterValue": "100000"
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
+        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
         "SampleAfterValue": "2000000",
@@ -28,6 +32,7 @@
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000000",
@@ -35,6 +40,7 @@
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
+        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000000",
@@ -42,12 +48,14 @@
     },
     {
         "BriefDescription": "SIMD Instructions retired.",
+        "Counter": "0,1",
         "EventCode": "0xCE",
         "EventName": "SIMD_INSTR_RETIRED",
         "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
+        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
         "SampleAfterValue": "2000000",
@@ -55,6 +63,7 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000000",
@@ -62,6 +71,7 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
+        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000000",
@@ -69,6 +79,7 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
+        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.VECTOR",
         "SampleAfterValue": "2000000",
@@ -76,12 +87,14 @@
     },
     {
         "BriefDescription": "Saturated arithmetic instructions retired.",
+        "Counter": "0,1",
         "EventCode": "0xCF",
         "EventName": "SIMD_SAT_INSTR_RETIRED",
         "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
+        "Counter": "0,1",
         "EventCode": "0xB1",
         "EventName": "SIMD_SAT_UOP_EXEC.AR",
         "SampleAfterValue": "2000000",
@@ -89,12 +102,14 @@
     },
     {
         "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
+        "Counter": "0,1",
         "EventCode": "0xB1",
         "EventName": "SIMD_SAT_UOP_EXEC.S",
         "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD micro-ops retired (excluding stores).",
+        "Counter": "0,1",
         "EventCode": "0xB0",
         "EventName": "SIMD_UOPS_EXEC.AR",
         "PEBS": "2",
@@ -103,12 +118,14 @@
     },
     {
         "BriefDescription": "SIMD micro-ops executed (excluding stores).",
+        "Counter": "0,1",
         "EventCode": "0xB0",
         "EventName": "SIMD_UOPS_EXEC.S",
         "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD packed arithmetic micro-ops retired",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
         "SampleAfterValue": "2000000",
@@ -116,6 +133,7 @@
     },
     {
         "BriefDescription": "SIMD packed arithmetic micro-ops executed",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
         "SampleAfterValue": "2000000",
@@ -123,6 +141,7 @@
     },
     {
         "BriefDescription": "SIMD packed logical micro-ops retired",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
         "SampleAfterValue": "2000000",
@@ -130,6 +149,7 @@
     },
     {
         "BriefDescription": "SIMD packed logical micro-ops executed",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
         "SampleAfterValue": "2000000",
@@ -137,6 +157,7 @@
     },
     {
         "BriefDescription": "SIMD packed multiply micro-ops retired",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
         "SampleAfterValue": "2000000",
@@ -144,6 +165,7 @@
     },
     {
         "BriefDescription": "SIMD packed multiply micro-ops executed",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
         "SampleAfterValue": "2000000",
@@ -151,6 +173,7 @@
     },
     {
         "BriefDescription": "SIMD packed micro-ops retired",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
         "SampleAfterValue": "2000000",
@@ -158,6 +181,7 @@
     },
     {
         "BriefDescription": "SIMD packed micro-ops executed",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
         "SampleAfterValue": "2000000",
@@ -165,6 +189,7 @@
     },
     {
         "BriefDescription": "SIMD packed shift micro-ops retired",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
         "SampleAfterValue": "2000000",
@@ -172,6 +197,7 @@
     },
     {
         "BriefDescription": "SIMD packed shift micro-ops executed",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
         "SampleAfterValue": "2000000",
@@ -179,6 +205,7 @@
     },
     {
         "BriefDescription": "SIMD unpacked micro-ops retired",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
         "SampleAfterValue": "2000000",
@@ -186,6 +213,7 @@
     },
     {
         "BriefDescription": "SIMD unpacked micro-ops executed",
+        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
         "SampleAfterValue": "2000000",
@@ -193,6 +221,7 @@
     },
     {
         "BriefDescription": "Floating point computational micro-ops retired.",
+        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.ANY.AR",
         "PEBS": "2",
@@ -201,6 +230,7 @@
     },
     {
         "BriefDescription": "Floating point computational micro-ops executed.",
+        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.ANY.S",
         "SampleAfterValue": "2000000",
@@ -208,6 +238,7 @@
     },
     {
         "BriefDescription": "FXCH uops retired.",
+        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
         "PEBS": "2",
@@ -216,6 +247,7 @@
     },
     {
         "BriefDescription": "FXCH uops executed.",
+        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.FXCH.S",
         "SampleAfterValue": "2000000",

tools/perf/pmu-events/arch/x86/bonnell/frontend.json

 [
     {
         "BriefDescription": "BACLEARS asserted.",
+        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
     },
     {
         "BriefDescription": "Cycles during which instruction fetches are  stalled.",
+        "Counter": "0,1",
         "EventCode": "0x86",
         "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
         "SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
     },
     {
         "BriefDescription": "Decode stall due to IQ full",
+        "Counter": "0,1",
         "EventCode": "0x87",
         "EventName": "DECODE_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
     },
     {
         "BriefDescription": "Decode stall due to PFB empty",
+        "Counter": "0,1",
         "EventCode": "0x87",
         "EventName": "DECODE_STALL.PFB_EMPTY",
         "SampleAfterValue": "2000000",
@@ -29,6 +33,7 @@
     },
     {
         "BriefDescription": "Instruction fetches.",
+        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
         "SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
     },
     {
         "BriefDescription": "Icache hit",
+        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
     },
     {
         "BriefDescription": "Icache miss",
+        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
     },
     {
         "BriefDescription": "All Instructions decoded",
+        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.ALL_DECODED",
         "SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
     },
     {
         "BriefDescription": "CISC macro instructions decoded",
+        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.CISC_DECODED",
         "SampleAfterValue": "2000000",
@@ -64,6 +73,7 @@
     },
     {
         "BriefDescription": "Non-CISC macro instructions decoded",
+        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.NON_CISC_DECODED",
         "SampleAfterValue": "2000000",
@@ -71,6 +81,7 @@
     },
     {
         "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
+        "Counter": "0,1",
         "CounterMask": "1",
         "EventCode": "0xA9",
         "EventName": "UOPS.MS_CYCLES",

tools/perf/pmu-events/arch/x86/bonnell/memory.json

 [
     {
         "BriefDescription": "Nonzero segbase 1 bubble",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.BUBBLE",
         "SampleAfterValue": "200000",
@@ -8,6 +9,7 @@
     },
     {
         "BriefDescription": "Nonzero segbase load 1 bubble",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
         "SampleAfterValue": "200000",
@@ -15,6 +17,7 @@
     },
     {
         "BriefDescription": "Load splits",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
         "SampleAfterValue": "200000",
@@ -22,6 +25,7 @@
     },
     {
         "BriefDescription": "Load splits (At Retirement)",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -29,6 +33,7 @@
     },
     {
         "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
         "SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
     },
     {
         "BriefDescription": "ld-op-st splits",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
         "SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
     },
     {
         "BriefDescription": "Memory references that cross an 8-byte boundary.",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.SPLIT",
         "SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
     },
     {
         "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -57,6 +65,7 @@
     },
     {
         "BriefDescription": "Nonzero segbase store 1 bubble",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
         "SampleAfterValue": "200000",
@@ -64,6 +73,7 @@
     },
     {
         "BriefDescription": "Store splits",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
         "SampleAfterValue": "200000",
@@ -71,6 +81,7 @@
     },
     {
         "BriefDescription": "Store splits (Ar Retirement)",
+        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -78,6 +89,7 @@
     },
     {
         "BriefDescription": "L1 hardware prefetch request",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.HW_PREFETCH",
         "SampleAfterValue": "2000000",
@@ -85,6 +97,7 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHNTA",
         "SampleAfterValue": "200000",
@@ -92,6 +105,7 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT0",
         "SampleAfterValue": "200000",
@@ -99,6 +113,7 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT1",
         "SampleAfterValue": "200000",
@@ -106,6 +121,7 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT2",
         "SampleAfterValue": "200000",
@@ -113,6 +129,7 @@
     },
     {
         "BriefDescription": "Any Software prefetch",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SOFTWARE_PREFETCH",
         "SampleAfterValue": "200000",
@@ -120,6 +137,7 @@
     },
     {
         "BriefDescription": "Any Software prefetch",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
         "SampleAfterValue": "200000",
@@ -127,6 +145,7 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SW_L2",
         "SampleAfterValue": "200000",

tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json

 [
     {
         "BriefDescription": "Memory accesses that missed the DTLB.",
+        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS",
         "SampleAfterValue": "200000",
@@ -8,6 +9,7 @@
     },
     {
         "BriefDescription": "DTLB misses due to load operations.",
+        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
         "SampleAfterValue": "200000",
@@ -15,6 +17,7 @@
     },
     {
         "BriefDescription": "DTLB misses due to store operations.",
+        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
         "SampleAfterValue": "200000",
@@ -22,6 +25,7 @@
     },
     {
         "BriefDescription": "L0 DTLB misses due to load operations.",
+        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
         "SampleAfterValue": "200000",
@@ -29,6 +33,7 @@
     },
     {
         "BriefDescription": "L0 DTLB misses due to store operations",
+        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
         "SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
     },
     {
         "BriefDescription": "ITLB flushes.",
+        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.FLUSH",
         "SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
     },
     {
         "BriefDescription": "ITLB hits.",
+        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
     },
     {
         "BriefDescription": "ITLB misses.",
+        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.MISSES",
         "PEBS": "2",
@@ -58,6 +66,7 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (precise event).",
+        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -66,6 +75,7 @@
     },
     {
         "BriefDescription": "Duration of page-walks in core cycles",
+        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.CYCLES",
         "SampleAfterValue": "2000000",
@@ -73,6 +83,7 @@
     },
     {
         "BriefDescription": "Duration of D-side only page walks",
+        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -80,6 +91,7 @@
     },
     {
         "BriefDescription": "Number of D-side only page walks",
+        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.D_SIDE_WALKS",
         "SampleAfterValue": "200000",
@@ -87,6 +99,7 @@
     },
     {
         "BriefDescription": "Duration of I-Side page walks",
+        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -94,6 +107,7 @@
     },
     {
         "BriefDescription": "Number of I-Side page walks",
+        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.I_SIDE_WALKS",
         "SampleAfterValue": "200000",
@@ -101,6 +115,7 @@
     },
     {
         "BriefDescription": "Number of page-walks executed.",
+        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.WALKS",
         "SampleAfterValue": "200000",