Commit 1965de63 authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Extract intel_cdclk_state

Use the same structure to store the cdclk state in both
intel_atomic_state and dev_priv. First step towards proper
old vs. new cdclk states.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-10-ville.syrjala@linux.intel.comReviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
parent 5604e9ce
......@@ -159,6 +159,8 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
struct intel_plane *plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct intel_cdclk_state *cdclk_state =
&dev_priv->cdclk_state;
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
......@@ -182,12 +184,12 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
* safe as long we hold at least one crtc mutex (which
* must be true since we have crtc_state).
*/
if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) {
if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
plane->base.base.id, plane->base.name,
crtc_state->min_cdclk[plane->id],
dev_priv->cdclk.logical.cdclk);
cdclk_state->logical.cdclk);
return true;
}
......
......@@ -824,8 +824,8 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
state->acquire_ctx = &ctx;
retry:
to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
to_intel_atomic_state(state)->cdclk.force_min_cdclk =
to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
enable ? 2 * 96000 : 0;
/* Protects dev_priv->cdclk.force_min_cdclk */
......
This diff is collapsed.
......@@ -7531,6 +7531,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
struct intel_cdclk_state *cdclk_state =
&dev_priv->cdclk_state;
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum intel_display_power_domain domain;
......@@ -7599,8 +7601,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
crtc->enabled_power_domains = 0;
dev_priv->active_pipes &= ~BIT(pipe);
dev_priv->cdclk.min_cdclk[pipe] = 0;
dev_priv->cdclk.min_voltage_level[pipe] = 0;
cdclk_state->min_cdclk[pipe] = 0;
cdclk_state->min_voltage_level[pipe] = 0;
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
......@@ -7845,6 +7847,8 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
to_i915(crtc_state->uapi.crtc->dev);
struct intel_atomic_state *intel_state =
to_intel_atomic_state(crtc_state->uapi.state);
const struct intel_cdclk_state *cdclk_state =
&intel_state->cdclk_state;
if (!hsw_crtc_state_ips_capable(crtc_state))
return false;
......@@ -7864,7 +7868,7 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
if (IS_BROADWELL(dev_priv) &&
crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
return false;
return true;
......@@ -12688,12 +12692,14 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
to_intel_atomic_state(crtc_state->uapi.state);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
const struct intel_cdclk_state *cdclk_state =
&state->cdclk_state;
if (!crtc_state->hw.enable)
return 0;
return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
state->cdclk.logical.cdclk);
cdclk_state->logical.cdclk);
}
static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
......@@ -14941,7 +14947,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
any_ms |= state->cdclk.force_min_cdclk_changed;
any_ms |= state->cdclk_state.force_min_cdclk_changed;
ret = intel_atomic_check_planes(state, &any_ms);
if (ret)
......@@ -14952,7 +14958,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
} else {
state->cdclk.logical = dev_priv->cdclk.logical;
state->cdclk_state.logical = dev_priv->cdclk_state.logical;
}
ret = intel_atomic_check_crtcs(state);
......@@ -17569,9 +17575,12 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
struct intel_cdclk_state *cdclk_state =
&i915->cdclk_state;
intel_update_cdclk(i915);
intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
}
static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
......@@ -18428,6 +18437,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
for_each_intel_crtc(dev, crtc) {
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
struct intel_cdclk_state *cdclk_state =
&dev_priv->cdclk_state;
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
......@@ -18497,8 +18508,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
min_cdclk = 0;
}
dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk;
dev_priv->cdclk.min_voltage_level[crtc->pipe] =
cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
cdclk_state->min_voltage_level[crtc->pipe] =
crtc_state->min_voltage_level;
intel_bw_crtc_update(bw_state, crtc_state);
......
......@@ -462,31 +462,7 @@ struct intel_atomic_state {
intel_wakeref_t wakeref;
struct {
/*
* Logical configuration of cdclk (used for all scaling,
* watermark, etc. calculations and checks). This is
* computed as if all enabled crtcs were active.
*/
struct intel_cdclk_config logical;
/*
* Actual configuration of cdclk, can be different from the
* logical configuration only when all crtc's are DPMS off.
*/
struct intel_cdclk_config actual;
int force_min_cdclk;
bool force_min_cdclk_changed;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
/* minimum acceptable voltage level for each pipe */
u8 min_voltage_level[I915_MAX_PIPES];
/* pipe to which cd2x update is synchronized */
enum pipe pipe;
} cdclk;
struct intel_cdclk_state cdclk_state;
bool dpll_set, modeset;
......@@ -514,9 +490,7 @@ struct intel_atomic_state {
/*
* active_pipes
* min_cdclk[]
* min_voltage_level[]
* cdclk.*
* cdclk_state
*/
bool global_state_changed;
......
......@@ -65,6 +65,7 @@
#include "i915_utils.h"
#include "display/intel_bios.h"
#include "display/intel_cdclk.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
......@@ -887,6 +888,33 @@ struct i915_selftest_stash {
atomic_t counter;
};
struct intel_cdclk_state {
/*
* Logical configuration of cdclk (used for all scaling,
* watermark, etc. calculations and checks). This is
* computed as if all enabled crtcs were active.
*/
struct intel_cdclk_config logical;
/*
* Actual configuration of cdclk, can be different from the
* logical configuration only when all crtc's are DPMS off.
*/
struct intel_cdclk_config actual;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
/* minimum acceptable voltage level for each pipe */
u8 min_voltage_level[I915_MAX_PIPES];
/* pipe to which cd2x update is synchronized */
enum pipe pipe;
/* forced minimum cdclk for glk+ audio w/a */
int force_min_cdclk;
bool force_min_cdclk_changed;
};
struct drm_i915_private {
struct drm_device drm;
......@@ -1007,29 +1035,14 @@ struct drm_i915_private {
* For reading holding any crtc lock is sufficient,
* for writing must hold all of them.
*/
struct intel_cdclk_state cdclk_state;
struct {
/*
* The current logical cdclk configuration.
* See intel_atomic_state.cdclk.logical
*/
struct intel_cdclk_config logical;
/*
* The current actual cdclk configuration.
* See intel_atomic_state.cdclk.actual
*/
struct intel_cdclk_config actual;
/* The current hardware cdclk configuration */
struct intel_cdclk_config hw;
/* cdclk, divider, and ratio table from bspec */
const struct intel_cdclk_vals *table;
int force_min_cdclk;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
/* minimum acceptable voltage level for each pipe */
u8 min_voltage_level[I915_MAX_PIPES];
} cdclk;
/**
......@@ -1086,8 +1099,8 @@ struct drm_i915_private {
struct mutex dpll_lock;
/*
* For reading active_pipes, min_cdclk, min_voltage_level holding
* any crtc lock is sufficient, for writing must hold all of them.
* For reading active_pipes, cdclk_state holding any crtc
* lock is sufficient, for writing must hold all of them.
*/
u8 active_pipes;
......
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