ARM: dts: imx53: Fix display pinmux for M53EVK

Use the DISP1 pinmux on M53EVK for the LCD, not the LVDS.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

arch/arm/boot/dts/imx53-m53evk.dts

@@ -26,7 +26,7 @@ display@di1 {
 			crtcs = <&ipu 1>;
 			interface-pix-fmt = "bgr666";
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_ipu_disp2>;
+			pinctrl-0 = <&pinctrl_ipu_disp1>;
 
 			display-timings {
 				800x480p60 {
@@ -292,18 +292,40 @@ MX53_PAD_GPIO_5__I2C3_SCL		0xc0000000
 			>;
 		};
 
-		pinctrl_ipu_disp2: ipudisp2grp {
+		pinctrl_ipu_disp1: ipudisp1grp {
 			fsl,pins = <
-				MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0	0x80000000
-				MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1	0x80000000
-				MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2	0x80000000
-				MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3	0x80000000
-				MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK	0x80000000
-				MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0	0x80000000
-				MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1	0x80000000
-				MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2	0x80000000
-				MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3	0x80000000
-				MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK	0x80000000
+				MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0	0x5
+				MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1	0x5
+				MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2	0x5
+				MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3	0x5
+				MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4	0x5
+				MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5	0x5
+				MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6	0x5
+				MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7	0x5
+				MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8	0x5
+				MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9	0x5
+				MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10	0x5
+				MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11	0x5
+				MX53_PAD_EIM_A17__IPU_DISP1_DAT_12	0x5
+				MX53_PAD_EIM_A18__IPU_DISP1_DAT_13	0x5
+				MX53_PAD_EIM_A19__IPU_DISP1_DAT_14	0x5
+				MX53_PAD_EIM_A20__IPU_DISP1_DAT_15	0x5
+				MX53_PAD_EIM_A21__IPU_DISP1_DAT_16	0x5
+				MX53_PAD_EIM_A22__IPU_DISP1_DAT_17	0x5
+				MX53_PAD_EIM_A23__IPU_DISP1_DAT_18	0x5
+				MX53_PAD_EIM_A24__IPU_DISP1_DAT_19	0x5
+				MX53_PAD_EIM_D31__IPU_DISP1_DAT_20	0x5
+				MX53_PAD_EIM_D30__IPU_DISP1_DAT_21	0x5
+				MX53_PAD_EIM_D26__IPU_DISP1_DAT_22	0x5
+				MX53_PAD_EIM_D27__IPU_DISP1_DAT_23	0x5
+				MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK	0x5
+				MX53_PAD_EIM_DA13__IPU_DI1_D0_CS	0x5
+				MX53_PAD_EIM_DA14__IPU_DI1_D1_CS	0x5
+				MX53_PAD_EIM_DA15__IPU_DI1_PIN1		0x5
+				MX53_PAD_EIM_DA11__IPU_DI1_PIN2		0x5
+				MX53_PAD_EIM_DA12__IPU_DI1_PIN3		0x5
+				MX53_PAD_EIM_A25__IPU_DI1_PIN12		0x5
+				MX53_PAD_EIM_DA10__IPU_DI1_PIN15	0x5
 			>;
 		};