Commit 19f4a055 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark

drm/msm/dsi_pll_7nm: Solve TODO for multiplier frac_bits assignment

The number of fractional registers bits is known and already set in
the frac_bits variable of the dsi_pll_config struct here in 7nm:
remove the TODO by simply using that variable. This is a copy of
196145eb ("drm/msm/dsi_pll_10nm: Solve TODO for multiplier frac_bits
assignment").
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 3b24cdfc
...@@ -509,6 +509,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, ...@@ -509,6 +509,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
{ {
struct msm_dsi_pll *pll = hw_clk_to_pll(hw); struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
struct dsi_pll_config *config = &pll_7nm->pll_configuration;
void __iomem *base = pll_7nm->mmio; void __iomem *base = pll_7nm->mmio;
u64 ref_clk = pll_7nm->vco_ref_clk_rate; u64 ref_clk = pll_7nm->vco_ref_clk_rate;
u64 vco_rate = 0x0; u64 vco_rate = 0x0;
...@@ -529,9 +530,8 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, ...@@ -529,9 +530,8 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
/* /*
* TODO: * TODO:
* 1. Assumes prescaler is disabled * 1. Assumes prescaler is disabled
* 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits)
*/ */
multiplier = 1 << 18; multiplier = 1 << config->frac_bits;
pll_freq = dec * (ref_clk * 2); pll_freq = dec * (ref_clk * 2);
tmp64 = (ref_clk * 2 * frac); tmp64 = (ref_clk * 2 * frac);
pll_freq += div_u64(tmp64, multiplier); pll_freq += div_u64(tmp64, multiplier);
......
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