Commit 1a8ca750 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie

drm/radeon: fix gpu_init on si

- Properly set up the RBs
- Properly set up the SPI
- Properly set up gb_addr_config

This should fix rendering issues on certain cards.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 7838e05a
...@@ -1374,9 +1374,9 @@ struct cayman_asic { ...@@ -1374,9 +1374,9 @@ struct cayman_asic {
struct si_asic { struct si_asic {
unsigned max_shader_engines; unsigned max_shader_engines;
unsigned max_pipes_per_simd;
unsigned max_tile_pipes; unsigned max_tile_pipes;
unsigned max_simds_per_se; unsigned max_cu_per_sh;
unsigned max_sh_per_se;
unsigned max_backends_per_se; unsigned max_backends_per_se;
unsigned max_texture_channel_caches; unsigned max_texture_channel_caches;
unsigned max_gprs; unsigned max_gprs;
...@@ -1387,7 +1387,6 @@ struct si_asic { ...@@ -1387,7 +1387,6 @@ struct si_asic {
unsigned sc_hiz_tile_fifo_size; unsigned sc_hiz_tile_fifo_size;
unsigned sc_earlyz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_size;
unsigned num_shader_engines;
unsigned num_tile_pipes; unsigned num_tile_pipes;
unsigned num_backends_per_se; unsigned num_backends_per_se;
unsigned backend_disable_mask_per_asic; unsigned backend_disable_mask_per_asic;
......
...@@ -273,7 +273,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) ...@@ -273,7 +273,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
break; break;
case RADEON_INFO_MAX_PIPES: case RADEON_INFO_MAX_PIPES:
if (rdev->family >= CHIP_TAHITI) if (rdev->family >= CHIP_TAHITI)
value = rdev->config.si.max_pipes_per_simd; value = rdev->config.si.max_cu_per_sh;
else if (rdev->family >= CHIP_CAYMAN) else if (rdev->family >= CHIP_CAYMAN)
value = rdev->config.cayman.max_pipes_per_simd; value = rdev->config.cayman.max_pipes_per_simd;
else if (rdev->family >= CHIP_CEDAR) else if (rdev->family >= CHIP_CEDAR)
......
This diff is collapsed.
...@@ -24,6 +24,11 @@ ...@@ -24,6 +24,11 @@
#ifndef SI_H #ifndef SI_H
#define SI_H #define SI_H
#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
#define CG_MULT_THERMAL_STATUS 0x714 #define CG_MULT_THERMAL_STATUS 0x714
#define ASIC_MAX_TEMP(x) ((x) << 0) #define ASIC_MAX_TEMP(x) ((x) << 0)
#define ASIC_MAX_TEMP_MASK 0x000001ff #define ASIC_MAX_TEMP_MASK 0x000001ff
...@@ -408,6 +413,12 @@ ...@@ -408,6 +413,12 @@
#define SOFT_RESET_IA (1 << 15) #define SOFT_RESET_IA (1 << 15)
#define GRBM_GFX_INDEX 0x802C #define GRBM_GFX_INDEX 0x802C
#define INSTANCE_INDEX(x) ((x) << 0)
#define SH_INDEX(x) ((x) << 8)
#define SE_INDEX(x) ((x) << 16)
#define SH_BROADCAST_WRITES (1 << 29)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
#define SE_BROADCAST_WRITES (1 << 31)
#define GRBM_INT_CNTL 0x8060 #define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0) # define RDERR_INT_ENABLE (1 << 0)
...@@ -480,6 +491,8 @@ ...@@ -480,6 +491,8 @@
#define VGT_TF_MEMORY_BASE 0x89B8 #define VGT_TF_MEMORY_BASE 0x89B8
#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
#define INACTIVE_CUS_MASK 0xFFFF0000
#define INACTIVE_CUS_SHIFT 16
#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
#define PA_CL_ENHANCE 0x8A14 #define PA_CL_ENHANCE 0x8A14
...@@ -688,6 +701,12 @@ ...@@ -688,6 +701,12 @@
#define RLC_MC_CNTL 0xC344 #define RLC_MC_CNTL 0xC344
#define RLC_UCODE_CNTL 0xC348 #define RLC_UCODE_CNTL 0xC348
#define PA_SC_RASTER_CONFIG 0x28350
# define RASTER_CONFIG_RB_MAP_0 0
# define RASTER_CONFIG_RB_MAP_1 1
# define RASTER_CONFIG_RB_MAP_2 2
# define RASTER_CONFIG_RB_MAP_3 3
#define VGT_EVENT_INITIATOR 0x28a90 #define VGT_EVENT_INITIATOR 0x28a90
# define SAMPLE_STREAMOUTSTATS1 (1 << 0) # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
# define SAMPLE_STREAMOUTSTATS2 (2 << 0) # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
......
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