Commit 1a91e318 authored by Stephen Boyd's avatar Stephen Boyd

Merge branches 'clk-fallthru', 'clk-ingenic', 'clk-tegra', 'clk-sirf' and 'clk-qoriq' into clk-next

 - Add RTC related clks on Ingenic SoCs
 - Support USB PHY clks on Ingenic SoCs

* clk-fallthru:
  clk: davinci: Use fallthrough pseudo-keyword
  clk: imx: Use fallthrough pseudo-keyword

* clk-ingenic:
  clk: X1000: Add support for calculat REFCLK of USB PHY.
  clk: JZ4780: Reformat the code to align it.
  clk: JZ4780: Add functions for enable and disable USB PHY.
  clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
  dt-bindings: clock: Add tabs to align code.
  dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.

* clk-tegra:
  clk: tegra: pll: Improve PLLM enable-state detection

* clk-sirf:
  clk: clk-atlas6: fix return value check in atlas6_clk_init()

* clk-qoriq:
  clk: qoriq: add LS1021A core pll mux options
......@@ -244,6 +244,14 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
},
};
static const struct clockgen_muxinfo ls1021a_cmux = {
{
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
}
};
static const struct clockgen_muxinfo ls1028a_hwa1 = {
{
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
......@@ -577,7 +585,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
{
.compat = "fsl,ls1021a-clockgen",
.cmux_groups = {
&t1023_cmux
&ls1021a_cmux
},
.cmux_to_group = {
0, -1
......
......@@ -651,7 +651,7 @@ static int davinci_pll_sysclk_rate_change(struct notifier_block *nb,
pllcmd = readl(pll->base + PLLCMD);
pllcmd |= PLLCMD_GOSET;
writel(pllcmd, pll->base + PLLCMD);
/* fallthrough */
fallthrough;
case PRE_RATE_CHANGE:
/* Wait until for outstanding changes to take effect */
do {
......
......@@ -433,7 +433,7 @@ struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
break;
case IMX_PLLV3_USB_VF610:
pll->div_shift = 1;
/* fall through */
fallthrough;
case IMX_PLLV3_USB:
ops = &clk_pllv3_ops;
pll->powerup_set = true;
......@@ -441,7 +441,7 @@ struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
case IMX_PLLV3_AV_IMX7:
pll->num_offset = PLL_IMX7_NUM_OFFSET;
pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
/* fall through */
fallthrough;
case IMX_PLLV3_AV:
ops = &clk_pllv3_av_ops;
break;
......
......@@ -4,6 +4,7 @@
*
* Copyright (c) 2013-2015 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
* Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#include <linux/clk-provider.h>
......@@ -59,6 +60,7 @@
#define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23)
#define USBPCR_POR BIT(22)
#define USBPCR_SIDDQ BIT(21)
#define USBPCR_OTG_DISABLE BIT(20)
#define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
#define USBPCR_OTGTUNE_MASK (0x7 << 14)
......@@ -100,32 +102,6 @@
static struct ingenic_cgu *cgu;
static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
{
/* we only use CLKCORE, revisit if that ever changes */
return 0;
}
static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx)
{
unsigned long flags;
u32 usbpcr1;
if (idx > 0)
return -EINVAL;
spin_lock_irqsave(&cgu->lock, flags);
usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;
/* we only use CLKCORE */
usbpcr1 |= USBPCR1_REFCLKSEL_CORE;
writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
spin_unlock_irqrestore(&cgu->lock, flags);
return 0;
}
static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
......@@ -149,7 +125,6 @@ static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
return 19200000;
}
BUG();
return parent_rate;
}
......@@ -206,13 +181,43 @@ static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
return 0;
}
static const struct clk_ops jz4780_otg_phy_ops = {
.get_parent = jz4780_otg_phy_get_parent,
.set_parent = jz4780_otg_phy_set_parent,
static int jz4780_otg_phy_enable(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
return 0;
}
static void jz4780_otg_phy_disable(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
}
static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
return (readl(reg_opcr) & OPCR_SPENDN0) &&
!(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
!(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
}
static const struct clk_ops jz4780_otg_phy_ops = {
.recalc_rate = jz4780_otg_phy_recalc_rate,
.round_rate = jz4780_otg_phy_round_rate,
.set_rate = jz4780_otg_phy_set_rate,
.enable = jz4780_otg_phy_enable,
.disable = jz4780_otg_phy_disable,
.is_enabled = jz4780_otg_phy_is_enabled,
};
static int jz4780_core1_enable(struct clk_hw *hw)
......@@ -516,6 +521,18 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR0, 1 },
},
[JZ4780_CLK_EXCLK_DIV512] = {
"exclk_div512", CGU_CLK_FIXDIV,
.parents = { JZ4780_CLK_EXCLK },
.fixdiv = { 512 },
},
[JZ4780_CLK_RTC] = {
"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
.parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK },
.mux = { CGU_REG_OPCR, 2, 1},
},
/* Gate-only clocks */
[JZ4780_CLK_NEMC] = {
......
......@@ -48,8 +48,87 @@
#define USBPCR_SIDDQ BIT(21)
#define USBPCR_OTG_DISABLE BIT(20)
/* bits within the USBPCR1 register */
#define USBPCR1_REFCLKSEL_SHIFT 26
#define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
#define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
#define USBPCR1_REFCLKDIV_SHIFT 24
#define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
static struct ingenic_cgu *cgu;
static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
u32 usbpcr1;
unsigned refclk_div;
usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
switch (refclk_div) {
case USBPCR1_REFCLKDIV_12:
return 12000000;
case USBPCR1_REFCLKDIV_24:
return 24000000;
case USBPCR1_REFCLKDIV_48:
return 48000000;
}
return parent_rate;
}
static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
unsigned long *parent_rate)
{
if (req_rate < 18000000)
return 12000000;
if (req_rate < 36000000)
return 24000000;
return 48000000;
}
static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
unsigned long parent_rate)
{
unsigned long flags;
u32 usbpcr1, div_bits;
switch (req_rate) {
case 12000000:
div_bits = USBPCR1_REFCLKDIV_12;
break;
case 24000000:
div_bits = USBPCR1_REFCLKDIV_24;
break;
case 48000000:
div_bits = USBPCR1_REFCLKDIV_48;
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&cgu->lock, flags);
usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
usbpcr1 |= div_bits;
writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
spin_unlock_irqrestore(&cgu->lock, flags);
return 0;
}
static int x1000_usb_phy_enable(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
......@@ -80,6 +159,10 @@ static int x1000_usb_phy_is_enabled(struct clk_hw *hw)
}
static const struct clk_ops x1000_otg_phy_ops = {
.recalc_rate = x1000_otg_phy_recalc_rate,
.round_rate = x1000_otg_phy_round_rate,
.set_rate = x1000_otg_phy_set_rate,
.enable = x1000_usb_phy_enable,
.disable = x1000_usb_phy_disable,
.is_enabled = x1000_usb_phy_is_enabled,
......@@ -144,7 +227,6 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
},
},
/* Custom (SoC-specific) OTG PHY */
[X1000_CLK_OTGPHY] = {
......@@ -278,6 +360,19 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.mux = { CGU_REG_SSICDR, 30, 1 },
},
[X1000_CLK_EXCLK_DIV512] = {
"exclk_div512", CGU_CLK_FIXDIV,
.parents = { X1000_CLK_EXCLK },
.fixdiv = { 512 },
},
[X1000_CLK_RTC] = {
"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
.parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
.mux = { CGU_REG_OPCR, 2, 1},
.gate = { CGU_REG_CLKGR, 27 },
},
/* Gate-only clocks */
[X1000_CLK_EMC] = {
......
......@@ -329,6 +329,19 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
.mux = { CGU_REG_SSICDR, 29, 1 },
},
[X1830_CLK_EXCLK_DIV512] = {
"exclk_div512", CGU_CLK_FIXDIV,
.parents = { X1830_CLK_EXCLK },
.fixdiv = { 512 },
},
[X1830_CLK_RTC] = {
"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
.parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK },
.mux = { CGU_REG_OPCR, 2, 1},
.gate = { CGU_REG_CLKGR0, 29 },
},
/* Gate-only clocks */
[X1830_CLK_EMC] = {
......
......@@ -135,7 +135,7 @@ static void __init atlas6_clk_init(struct device_node *np)
for (i = pll1; i < maxclk; i++) {
atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
BUG_ON(!atlas6_clks[i]);
BUG_ON(IS_ERR(atlas6_clks[i]));
}
clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
clk_register_clkdev(atlas6_clks[io], NULL, "io");
......
......@@ -327,16 +327,26 @@ int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
return clk_pll_wait_for_lock(pll);
}
static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
{
u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
!(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
}
static int clk_pll_is_enabled(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
u32 val;
if (pll->params->flags & TEGRA_PLLM) {
val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
}
/*
* Power Management Controller (PMC) can override the PLLM clock
* settings, including the enable-state. The PLLM is enabled when
* PLLM's CaR state is ON and when PLLM isn't gated by PMC.
*/
if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
return 0;
val = pll_readl_base(pll);
......
......@@ -85,5 +85,7 @@
#define JZ4780_CLK_DES 70
#define JZ4780_CLK_X2D 71
#define JZ4780_CLK_CORE1 72
#define JZ4780_CLK_EXCLK_DIV512 73
#define JZ4780_CLK_RTC 74
#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
......@@ -48,5 +48,7 @@
#define X1000_CLK_SSI 33
#define X1000_CLK_OST 34
#define X1000_CLK_PDMA 35
#define X1000_CLK_EXCLK_DIV512 36
#define X1000_CLK_RTC 37
#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
......@@ -51,5 +51,7 @@
#define X1830_CLK_TCU 36
#define X1830_CLK_DTRNG 37
#define X1830_CLK_OST 38
#define X1830_CLK_EXCLK_DIV512 39
#define X1830_CLK_RTC 40
#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
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