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Commit 1afa9c3b authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM Device-tree updates from Olof Johansson:
 "New SoCs:

   - Atmel/Microchip SAM9X60 (ARM926 SoC)

   - OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all
     variants of it with different GPU/media IP configurations.

   - ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)

   - ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of
     db8500)

   - Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)

   - Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)

  New boards:

   - Allwinner:
      + Emlid Neutis SoM (H3 variant)
      + Libre Computer ALL-H3-IT
      + PineH64 Model B

   - Amlogic:
      + Libretech Amlogic GX PC (s905d and s912-based variants)

   - Atmel/Microchip:
      + Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)

   - Marvell:
      + Armada 385-based SolidRun Clearfog GTR

   - NXP:
      + Gateworks GW59xx boards based on i.MX6/6Q/6QDL
      + Tolino Shine 3 eBook reader (i.MX6sl)
      + Embedded Artists COM (i.MX7ULP)
      + SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
      + Google Coral Edge TPU (i.MX8MQ)

   - Rockchip:
      + Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
      + Radxa Rock Pi N10 (RK3399Pro-based)
      + VMARC RK3399Pro SOM

   - ST:
      + Reference boards for stm32mp15

   - ST Ericsson:
      + Samsung Galaxy S III mini (GT-I8190)
      + HREF520 reference board for DB8520

   - TI OMAP:
      + Gen1 Amazon Echo (OMAP3630-based)

   - Qualcomm:
      + Inforce 6640 Single Board Computer (msm8996-based)
      + SC7180 IDP (SC7180-based)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits)
  dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml
  arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera
  arm64: dts: ti: k3-am65-main Add CAL node
  arm64: dts: ti: k3-j721e-main: Add McASP nodes
  arm64: dts: ti: k3-am654-main: Add McASP nodes
  arm64: dts: ti: k3-j721e: DMA support
  arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss
  arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation
  arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS
  arm64: dts: ti: k3-am65: DMA support
  arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss
  arm64: dts: ti: k3-am65-main: Correct main NAVSS representation
  ARM: dts: aspeed: rainier: Add UCD90320 power sequencer
  ARM: dts: aspeed: rainier: Switch PSUs to unknown version
  arm64: dts: rockchip: Kill off "simple-panel" compatibles
  ARM: dts: rockchip: Kill off "simple-panel" compatibles
  arm64: dts: rockchip: rename dwmmc node names to mmc
  ARM: dts: rockchip: rename dwmmc node names to mmc
  arm64: dts: exynos: Rename Samsung and Exynos to lowercase
  arm64: dts: uniphier: add reset-names to NAND controller node
  ...
parents 469030d4 d030a0dd
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Documentation/devicetree/bindings/arm/amlogic.yaml
View file @ 1afa9c3b
......@@ -59,6 +59,7 @@ properties:
- friendlyarm,nanopi-k2
- hardkernel,odroid-c2
- nexbox,a95x
- videostrong,kii-pro
- wetek,hub
- wetek,play2
- const: amlogic,meson-gxbb
......@@ -104,6 +105,7 @@ properties:
- enum:
- amlogic,p230
- amlogic,p231
- libretech,aml-s905d-pc
- phicomm,n1
- const: amlogic,s905d
- const: amlogic,meson-gxl
......@@ -115,6 +117,7 @@ properties:
- amlogic,q201
- khadas,vim2
- kingnovel,r-box-pro
- libretech,aml-s912-pc
- nexbox,a1
- tronsmart,vega-s96
- const: amlogic,s912
......
Documentation/devicetree/bindings/arm/atmel-at91.yaml
View file @ 1afa9c3b
......@@ -35,6 +35,16 @@ properties:
- atmel,at91sam9x60
- const: atmel,at91sam9
- items:
- enum:
- overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board
- overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board
- overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN
- overkiz,smartkiz # Overkiz SmartKiz Board
- const: atmel,at91sam9g25
- const: atmel,at91sam9x5
- const: atmel,at91sam9
- items:
- enum:
- atmel,at91sam9g15
......@@ -52,11 +62,32 @@ properties:
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D27 WLSOM1
items:
- const: microchip,sama5d27-wlsom1
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D27 WLSOM1 Evaluation Kit
items:
- const: microchip,sama5d27-wlsom1-ek
- const: microchip,sama5d27-wlsom1
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- items:
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: SAM9X60-EK board
items:
- const: microchip,sam9x60ek
- const: microchip,sam9x60
- const: atmel,at91sam9
- description: Nattis v2 board with Natte v2 power board
items:
- const: axentia,nattis-2
......
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
View file @ 1afa9c3b
......@@ -45,6 +45,7 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
"microchip,sam9x60-ddramc"
- reg: Should contain registers location and length
Examples:
......
Documentation/devicetree/bindings/arm/fsl.yaml
View file @ 1afa9c3b
......@@ -128,6 +128,27 @@ properties:
- variscite,dt6customboard
- const: fsl,imx6q
- description: i.MX6Q Gateworks Ventana Boards
items:
- enum:
- gw,imx6q-gw51xx
- gw,imx6q-gw52xx
- gw,imx6q-gw53xx
- gw,imx6q-gw5400-a
- gw,imx6q-gw54xx
- gw,imx6q-gw551x
- gw,imx6q-gw552x
- gw,imx6q-gw553x
- gw,imx6q-gw560x
- gw,imx6q-gw5903
- gw,imx6q-gw5904
- gw,imx6q-gw5907
- gw,imx6q-gw5910
- gw,imx6q-gw5912
- gw,imx6q-gw5913
- const: gw,ventana
- const: fsl,imx6q
- description: i.MX6QP based Boards
items:
- enum:
......@@ -154,10 +175,31 @@ properties:
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
- const: fsl,imx6dl
- description: i.MX6DL Gateworks Ventana Boards
items:
- enum:
- gw,imx6dl-gw51xx
- gw,imx6dl-gw52xx
- gw,imx6dl-gw53xx
- gw,imx6dl-gw54xx
- gw,imx6dl-gw551x
- gw,imx6dl-gw552x
- gw,imx6dl-gw553x
- gw,imx6dl-gw560x
- gw,imx6dl-gw5903
- gw,imx6dl-gw5904
- gw,imx6dl-gw5907
- gw,imx6dl-gw5910
- gw,imx6dl-gw5912
- gw,imx6dl-gw5913
- const: gw,ventana
- const: fsl,imx6dl
- description: i.MX6SL based Boards
items:
- enum:
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
- kobo,tolino-shine3
- const: fsl,imx6sl
- description: i.MX6SLL based Boards
......@@ -172,6 +214,7 @@ properties:
- enum:
- fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
- fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
- fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board
- const: fsl,imx6sx
- description: i.MX6UL based Boards
......@@ -239,6 +282,7 @@ properties:
items:
- enum:
- fsl,imx7d-sdb # i.MX7 SabreSD Board
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
......@@ -263,6 +307,7 @@ properties:
- description: i.MX7ULP based Boards
items:
- enum:
- ea,imx7ulp-com # i.MX7ULP Embedded Artists COM Board
- fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit
- const: fsl,imx7ulp
......@@ -283,7 +328,9 @@ properties:
items:
- enum:
- boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- google,imx8mq-phanbell # Google Coral Edge TPU
- purism,librem5-devkit # Purism Librem5 devkit
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
......@@ -385,6 +432,13 @@ properties:
- fsl,ls2088a-rdb
- const: fsl,ls2088a
- description: LX2160A based Boards
items:
- enum:
- fsl,lx2160a-qds
- fsl,lx2160a-rdb
- const: fsl,lx2160a
- description: S32V234 based Boards
items:
- enum:
......
Documentation/devicetree/bindings/arm/qcom.yaml
View file @ 1afa9c3b
......@@ -24,28 +24,30 @@ description: |
The 'SoC' element must be one of the following strings:
apq8016
apq8074
apq8084
apq8096
msm8916
msm8974
msm8992
msm8994
msm8996
mdm9615
ipq8074
sdm845
apq8016
apq8074
apq8084
apq8096
ipq8074
mdm9615
msm8916
msm8974
msm8992
msm8994
msm8996
sc7180
sdm845
The 'board' element must be one of the following strings:
cdp
liquid
dragonboard
mtp
sbc
hk01
qrd
cdp
dragonboard
hk01
idp
liquid
mtp
qrd
sbc
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
......@@ -144,4 +146,8 @@ properties:
- qcom,ipq8074-hk01
- const: qcom,ipq8074
- items:
- enum:
- qcom,sc7180-idp
- const: qcom,sc7180
...
Documentation/devicetree/bindings/arm/rockchip.yaml
View file @ 1afa9c3b
......@@ -409,6 +409,9 @@ properties:
- description: Pine64 RockPro64
items:
- enum:
- pine64,rockpro64-v2.1
- pine64,rockpro64-v2.0
- const: pine64,rockpro64
- const: rockchip,rk3399
......@@ -422,6 +425,12 @@ properties:
- const: radxa,rockpi4
- const: rockchip,rk3399
- description: Radxa ROCK Pi N10
items:
- const: radxa,rockpi-n10
- const: vamrs,rk3399pro-vmarc-som
- const: rockchip,rk3399pro
- description: Radxa Rock2 Square
items:
- const: radxa,rock2-square
......
Documentation/devicetree/bindings/arm/sprd.yaml → Documentation/devicetree/bindings/arm/sprd/sprd.yaml
View file @ 1afa9c3b
......@@ -2,7 +2,7 @@
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sprd.yaml#
$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Unisoc platforms device tree bindings
......
Documentation/devicetree/bindings/arm/sunxi.yaml
View file @ 1afa9c3b
......@@ -342,6 +342,16 @@ properties:
- const: libretech,all-h3-cc-h5
- const: allwinner,sun50i-h5
- description: Libre Computer Board ALL-H3-IT H5
items:
- const: libretech,all-h3-it-h5
- const: allwinner,sun50i-h5
- description: Libre Computer Board ALL-H5-CC H5
items:
- const: libretech,all-h5-cc-h5
- const: allwinner,sun50i-h5
- description: Lichee Pi One
items:
- const: licheepi,licheepi-one
......@@ -470,6 +480,12 @@ properties:
- const: emlid,neutis-n5
- const: allwinner,sun50i-h5
- description: Emlid Neutis N5H3 Developper Board
items:
- const: emlid,neutis-n5h3-devboard
- const: emlid,neutis-n5h3
- const: allwinner,sun8i-h3
- description: NextThing Co. CHIP
items:
- const: nextthing,chip
......@@ -599,11 +615,16 @@ properties:
- const: pine64,pine64-plus
- const: allwinner,sun50i-a64
- description: Pine64 PineH64
- description: Pine64 PineH64 model A
items:
- const: pine64,pine-h64
- const: allwinner,sun50i-h6
- description: Pine64 PineH64 model B
items:
- const: pine64,pine-h64-model-b
- const: allwinner,sun50i-h6
- description: Pine64 LTS
items:
- const: pine64,pine64-lts
......
Documentation/devicetree/bindings/arm/ux500.yaml 0 → 100644
View file @ 1afa9c3b
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ux500.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ux500 platforms device tree bindings
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: ST-Ericsson HREF (pre-v60)
items:
- const: st-ericsson,mop500
- const: st-ericsson,u8500
- description: ST-Ericsson HREF (v60+)
items:
- const: st-ericsson,hrefv60+
- const: st-ericsson,u8500
- description: Calao Systems Snowball
items:
- const: calaosystems,snowball-a9500
- const: st-ericsson,u9500
- description: Samsung Galaxy S III mini (GT-I8190)
items:
- const: samsung,golden
- const: st-ericsson,u8500
Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml 0 → 100644
View file @ 1afa9c3b
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A83t Display Engine 2/3 Clock Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
oneOf:
- const: allwinner,sun8i-a83t-de2-clk
- const: allwinner,sun8i-h3-de2-clk
- const: allwinner,sun8i-v3s-de2-clk
- const: allwinner,sun50i-a64-de2-clk
- const: allwinner,sun50i-h5-de2-clk
- const: allwinner,sun50i-h6-de2-clk
- items:
- const: allwinner,sun8i-r40-de2-clk
- const: allwinner,sun8i-h3-de2-clk
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: bus
- const: mod
resets:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
de2_clocks: clock@1000000 {
compatible = "allwinner,sun8i-h3-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml 0 → 100644
View file @ 1afa9c3b
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-de-clks
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: RAM Bus Clock
- description: Module Clock
clock-names:
items:
- const: mod
- const: dram
- const: bus
resets:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
de_clocks: clock@3000000 {
compatible = "allwinner,sun9i-a80-de-clks";
reg = <0x03000000 0x30>;
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
clock-names = "mod", "dram", "bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml 0 → 100644
View file @ 1afa9c3b
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 USB Clock Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-usb-clocks
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: High Frequency Oscillator
clock-names:
items:
- const: bus
- const: hosc
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun9i-a80-ccu.h>
usb_clocks: clock@a08000 {
compatible = "allwinner,sun9i-a80-usb-clks";
reg = <0x00a08000 0x8>;
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
clock-names = "bus", "hosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/sun8i-de2.txt deleted 100644 → 0
View file @ 469030d4
Allwinner Display Engine 2.0/3.0 Clock Control Binding
------------------------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- "allwinner,sun50i-h6-de3-clk"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
Three are needed:
- "mod": the display engine module clock (on A83T it's the DE PLL)
- "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
de2_clocks: clock@1000000 {
compatible = "allwinner,sun8i-h3-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/clock/sun9i-de.txt deleted 100644 → 0
View file @ 469030d4
Allwinner A80 Display Engine Clock Control Binding
--------------------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun9i-a80-de-clks"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
Three are needed:
- "mod": the display engine module clock
- "dram": the DRAM bus clock for the system
- "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
de_clocks: clock@3000000 {
compatible = "allwinner,sun9i-a80-de-clks";
reg = <0x03000000 0x30>;
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
clock-names = "mod", "dram", "bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/clock/sun9i-usb.txt deleted 100644 → 0
View file @ 469030d4
Allwinner A80 USB Clock Control Binding
---------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun9i-a80-usb-clocks"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:
- "bus": the bus clock for the whole USB subsystem
- "hosc": the high frequency oscillator (usually at 24MHz)
- clock-names: Must contain the clock names described just above
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
usb_clocks: clock@a08000 {
compatible = "allwinner,sun9i-a80-usb-clks";
reg = <0x00a08000 0x8>;
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
clock-names = "bus", "hosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/display/mxsfb.txt
View file @ 1afa9c3b
......@@ -6,6 +6,7 @@ Required properties:
- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
Should be "fsl,imx28-lcdif" for i.MX28.
Should be "fsl,imx6sx-lcdif" for i.MX6SX.
Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
- reg: Address and length of the register set for LCDIF
- interrupts: Should contain LCDIF interrupt
- clocks: A list of phandle + clock-specifier pairs, one for each
......
Documentation/devicetree/bindings/dma/atmel-xdma.txt
View file @ 1afa9c3b
......@@ -2,9 +2,7 @@
* XDMA Controller
Required properties:
- compatible: Should be "atmel,<chip>-dma".
<chip> compatible description:
- sama5d4: first SoC adding the XDMAC
- compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain DMA interrupt.
- #dma-cells: Must be <1>, used to represent the number of integer cells in
......
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
View file @ 1afa9c3b
......@@ -18,6 +18,7 @@ properties:
- enum:
- amlogic,meson-g12a-mali
- realtek,rtd1619-mali
- rockchip,px30-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
reg:
......
Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
View file @ 1afa9c3b
* AT91 SAMA5D2 Analog to Digital Converter (ADC)
Required properties:
- compatible: Should be "atmel,sama5d2-adc".
- compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
- reg: Should contain ADC registers location and length.
- interrupts: Should contain the IRQ line for the ADC.
- clocks: phandle to device clock.
......
Documentation/devicetree/bindings/media/atmel-isi.txt
View file @ 1afa9c3b
......@@ -2,7 +2,7 @@ Atmel Image Sensor Interface (ISI)
----------------------------------
Required properties for ISI:
- compatible: must be "atmel,at91sam9g45-isi".
- compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
- reg: physical base address and length of the registers set for the device.
- interrupts: should contain IRQ line for the ISI.
- clocks: list of clock specifiers, corresponding to entries in the clock-names
......
Documentation/devicetree/bindings/media/fsl-pxp.txt
View file @ 1afa9c3b
......@@ -8,7 +8,7 @@ i.MX SoCs from i.MX23 to i.MX7.
Required properties:
- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
imx6dl, imx6sl, imx6ul, imx6sx, imx6ull, or imx7d.
imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
- reg: the register base and size for the device registers
- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
- clock-names: should be "axi"
......
Documentation/devicetree/bindings/media/rc.yaml
View file @ 1afa9c3b
......@@ -123,6 +123,7 @@ properties:
- rc-su3000
- rc-tango
- rc-tanix-tx3mini
- rc-tanix-tx5max
- rc-tbs-nec
- rc-technisat-ts35
- rc-technisat-usb2
......
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml 0 → 100644
View file @ 1afa9c3b
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) SoC Memory Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
handles memory requests for 40-bit virtual addresses from internal clients
and arbitrates among them to allocate memory bandwidth.
Up to 15 GiB of physical memory can be supported. Security features such as
encryption of traffic to and from DRAM via general security apertures are
available for video and other secure applications, as well as DRAM ECC for
automotive safety applications (single bit error correction and double bit
error detection).
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
items:
- enum:
- nvidia,tegra186-mc
- nvidia,tegra194-mc
reg:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
dma-ranges: true
patternProperties:
"^external-memory-controller@[0-9a-f]+$":
description:
The bulk of the work involved in controlling the external memory
controller on NVIDIA Tegra186 and later is performed on the BPMP. This
coprocessor exposes the EMC clock that is used to set the frequency at
which the external memory is clocked and a remote procedure call that
can be used to obtain the set of available frequencies.
type: object
properties:
compatible:
items:
- enum:
- nvidia,tegra186-emc
- nvidia,tegra194-emc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: external memory clock
clock-names:
items:
- const: emc
nvidia,bpmp:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the node representing the BPMP
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0xb0000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>;
/*
* Memory clients have access to all 40 bits that the memory
* controller can address.
*/
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
external-memory-controller@2c60000 {
compatible = "nvidia,tegra186-emc";
reg = <0x0 0x02c60000 0x0 0x50000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_EMC>;
clock-names = "emc";
nvidia,bpmp = <&bpmp>;
};
};
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
#clock-cells = <1>;
};
Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
View file @ 1afa9c3b
......@@ -3,7 +3,9 @@
The GPBR are a set of battery-backed registers.
Required properties:
- compatible: "atmel,at91sam9260-gpbr", "syscon"
- compatible: Should be one of the following:
"atmel,at91sam9260-gpbr", "syscon"
"microchip,sam9x60-gpbr", "syscon"
- reg: contains offset/length value of the GPBR memory
region.
......
Documentation/devicetree/bindings/mfd/atmel-matrix.txt
View file @ 1afa9c3b
......@@ -13,6 +13,7 @@ Required properties:
"atmel,at91sam9n12-matrix", "syscon"
"atmel,at91sam9x5-matrix", "syscon"
"atmel,sama5d3-matrix", "syscon"
"microchip,sam9x60-matrix", "syscon"
- reg: Contains offset/length value of the Bus Matrix
memory region.
......
Documentation/devicetree/bindings/mfd/atmel-smc.txt
View file @ 1afa9c3b
......@@ -9,6 +9,7 @@ Required properties:
"atmel,at91sam9260-smc", "syscon"
"atmel,sama5d3-smc", "syscon"
"atmel,sama5d2-smc", "syscon"
"microchip,sam9x60-smc", "syscon"
- reg: Contains offset/length value of the SMC memory
region.
......
Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt
View file @ 1afa9c3b
......@@ -18,6 +18,7 @@ Required properties:
Optional properties:
===================
- reg: A hint for the memory regions associated with the P2A controller
- memory-region: A phandle to a reserved_memory region to be used for the PCI
to AHB mapping
......
Documentation/devicetree/bindings/mtd/atmel-nand.txt
View file @ 1afa9c3b
......@@ -57,6 +57,7 @@ Required properties:
"atmel,at91sam9g45-pmecc"
"atmel,sama5d4-pmecc"
"atmel,sama5d2-pmecc"
"microchip,sam9x60-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
block, and the second one to the PMECC_ERRLOC block.
......
Documentation/devicetree/bindings/net/can/atmel-can.txt
View file @ 1afa9c3b
* AT91 CAN *
Required properties:
- compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can"
- compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
"microchip,sam9x60-can"
- reg: Should contain CAN controller registers location and length
- interrupts: Should contain IRQ line for the CAN controller
......
Documentation/devicetree/bindings/net/can/rcar_can.txt
View file @ 1afa9c3b
......@@ -7,6 +7,7 @@ Required properties:
"renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
"renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
"renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
"renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
"renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
"renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
"renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
......@@ -36,8 +37,8 @@ Required properties:
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must be "default".
Required properties for R8A774A1, R8A774C0, R8A7795, R8A7796, R8A77965,
R8A77990, and R8A77995:
Required properties for R8A774A1, R8A774B1, R8A774C0, R8A7795, R8A7796,
R8A77965, R8A77990, and R8A77995:
For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can
be used by both CAN and CAN FD controller at the same time. It needs to be
scaled to maximum frequency if any of these controllers use it. This is done
......
Documentation/devicetree/bindings/net/can/rcar_canfd.txt
View file @ 1afa9c3b
......@@ -5,6 +5,7 @@ Required properties:
- compatible: Must contain one or more of the following:
- "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
- "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
- "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
- "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
- "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
- "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
......@@ -31,8 +32,8 @@ The name of the child nodes are "channel0" and "channel1" respectively. Each
child node supports the "status" property only, which is used to
enable/disable the respective channel.
Required properties for R8A774A1, R8A774C0, R8A7795, R8A7796, R8A77965,
R8A77990, and R8A77995:
Required properties for R8A774A1, R8A774B1, R8A774C0, R8A7795, R8A7796,
R8A77965, R8A77990, and R8A77995:
In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN
and CAN FD controller at the same time. It needs to be scaled to maximum
frequency if any of these controllers use it. This is done using the below
......
Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml 0 → 100644
View file @ 1afa9c3b
# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright 2019 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Marvell MMP3 HSIC PHY
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
properties:
compatible:
const: marvell,mmp3-hsic-phy
reg:
maxItems: 1
description: base address of the device
reset-gpios:
maxItems: 1
description: GPIO connected to reset
"#phy-cells":
const: 0
required:
- compatible
- reg
- reset-gpios
- "#phy-cells"
examples:
- |
#include <dt-bindings/gpio/gpio.h>
hsic-phy@f0001800 {
compatible = "marvell,mmp3-hsic-phy";
reg = <0xf0001800 0x40>;
reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
#phy-cells = <0>;
};
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
View file @ 1afa9c3b
......@@ -22,6 +22,9 @@ description: |+
properties:
compatible:
const: aspeed,ast2400-pinctrl
reg:
description: |
A hint for the memory regions associated with the pin-controller
patternProperties:
'^.*$':
......
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View file @ 1afa9c3b
......@@ -23,6 +23,9 @@ description: |+
properties:
compatible:
const: aspeed,ast2500-pinctrl
reg:
description: |
A hint for the memory regions associated with the pin-controller
aspeed,external-nodes:
minItems: 2
maxItems: 2
......
Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
View file @ 1afa9c3b
......@@ -30,13 +30,51 @@ properties:
- items:
- const: allwinner,sun50i-h5-pwm
- const: allwinner,sun5i-a13-pwm
- const: allwinner,sun50i-h6-pwm
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
items:
- description: Module Clock
- description: Bus Clock
# Even though it only applies to subschemas under the conditionals,
# not listing them here will trigger a warning because of the
# additionalsProperties set to false.
clock-names: true
resets:
maxItems: 1
if:
properties:
compatible:
contains:
const: allwinner,sun50i-h6-pwm
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: mod
- const: bus
required:
- clock-names
- resets
else:
properties:
clocks:
maxItems: 1
required:
- "#pwm-cells"
- compatible
......@@ -54,4 +92,17 @@ examples:
#pwm-cells = <3>;
};
- |
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
pwm@300a000 {
compatible = "allwinner,sun50i-h6-pwm";
reg = <0x0300a000 0x400>;
clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
clock-names = "mod", "bus";
resets = <&ccu RST_BUS_PWM>;
#pwm-cells = <3>;
};
...
Documentation/devicetree/bindings/timer/renesas,tmu.txt
View file @ 1afa9c3b
......@@ -11,6 +11,7 @@ Required Properties:
- compatible: must contain one or more of the following:
- "renesas,tmu-r8a7740" for the r8a7740 TMU
- "renesas,tmu-r8a774a1" for the r8a774A1 TMU
- "renesas,tmu-r8a774b1" for the r8a774B1 TMU
- "renesas,tmu-r8a774c0" for the r8a774C0 TMU
- "renesas,tmu-r8a7778" for the r8a7778 TMU
- "renesas,tmu-r8a7779" for the r8a7779 TMU
......
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file @ 1afa9c3b
......@@ -1034,6 +1034,8 @@ patternProperties:
description: Variscite Ltd.
"^via,.*":
description: VIA Technologies, Inc.
"^videostrong,.*":
description: Videostrong Technology Co., Ltd.
"^virtio,.*":
description: Virtual I/O Device Specification, developed by the OASIS consortium
"^vishay,.*":
......
MAINTAINERS
View file @ 1afa9c3b
......@@ -2092,6 +2092,7 @@ F: drivers/rtc/rtc-pl031.c
F: drivers/watchdog/coh901327_wdt.c
F: Documentation/devicetree/bindings/arm/ste-*
F: Documentation/devicetree/bindings/arm/ux500/
F: Documentation/devicetree/bindings/arm/ux500.yaml
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
ARM/NUVOTON NPCM ARCHITECTURE
......
arch/arm/boot/dts/Makefile
View file @ 1afa9c3b
......@@ -37,18 +37,24 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91-ariag25.dtb \
at91-ariettag25.dtb \
at91-cosino_mega2560.dtb \
at91-kizboxmini.dtb \
at91-kizboxmini-base.dtb \
at91-kizboxmini-mb.dtb \
at91-kizboxmini-rd.dtb \
at91-smartkiz.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
at91sam9g25ek.dtb \
at91sam9g35ek.dtb \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM9X60) += \
at91-sam9x60ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2-2.dtb \
at91-kizbox3-hs.dtb \
at91-nattis-2-natte-2.dtb \
at91-sama5d27_som1_ek.dtb \
at91-sama5d27_wlsom1_ek.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
......@@ -422,6 +428,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw560x.dtb \
imx6dl-gw5903.dtb \
imx6dl-gw5904.dtb \
imx6dl-gw5907.dtb \
imx6dl-gw5910.dtb \
imx6dl-gw5912.dtb \
imx6dl-gw5913.dtb \
imx6dl-hummingboard.dtb \
imx6dl-hummingboard-emmc-som-v15.dtb \
imx6dl-hummingboard-som-v15.dtb \
......@@ -493,6 +503,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw560x.dtb \
imx6q-gw5903.dtb \
imx6q-gw5904.dtb \
imx6q-gw5907.dtb \
imx6q-gw5910.dtb \
imx6q-gw5912.dtb \
imx6q-gw5913.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-hummingboard-emmc-som-v15.dtb \
......@@ -554,6 +568,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-tolino-shine3.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb \
......@@ -612,6 +627,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7s-mba7.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
......@@ -691,6 +707,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
omap3-devkit8000.dtb \
omap3-devkit8000-lcd43.dtb \
omap3-devkit8000-lcd70.dtb \
omap3-echo.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-gta04a3.dtb \
......@@ -1129,6 +1146,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
sun8i-h3-rervision-dvk.dtb \
sun8i-h3-emlid-neutis-n5h3-devboard.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
......@@ -1182,7 +1200,9 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
ste-hrefv60plus-stuib.dtb \
ste-hrefv60plus-tvk.dtb
ste-hrefv60plus-tvk.dtb \
ste-href520-tvk.dtb \
ste-ux500-samsung-golden.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld4-ref.dtb \
uniphier-ld6b-ref.dtb \
......@@ -1238,6 +1258,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-clearfog-gtr-s4.dtb \
armada-385-clearfog-gtr-l8.dtb \
armada-385-db-88f6820-amc.dtb \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
......
arch/arm/boot/dts/am335x-evm.dts
View file @ 1afa9c3b
......@@ -113,7 +113,7 @@ switch10 {
};
};
backlight {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
......@@ -121,35 +121,15 @@ backlight {
};
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
compatible = "tfc,s9700rtwv43tr-01b";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins_s0>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
backlight = <&backlight>;
display-timings {
800x480p62 {
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <39>;
hback-porch = <39>;
hsync-len = <47>;
vback-porch = <29>;
vfront-porch = <13>;
vsync-len = <2>;
hsync-active = <1>;
vsync-active = <1>;
port {
panel_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
......@@ -500,6 +480,12 @@ &lcdc {
status = "okay";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&panel_0>;
};
};
};
&elm {
......
arch/arm/boot/dts/am335x-evmsk.dts
View file @ 1afa9c3b
......@@ -183,36 +183,16 @@ sound_master: simple-audio-card,codec {
};
panel {
compatible = "ti,tilcdc,panel";
compatible = "newhaven,nhd-4.3-480272ef-atxl";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
backlight = <&lcd_bl>;
status = "okay";
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
480x272 {
hactive = <480>;
vactive = <272>;
hback-porch = <43>;
hfront-porch = <8>;
hsync-len = <4>;
vback-porch = <12>;
vfront-porch = <4>;
vsync-len = <10>;
clock-frequency = <9000000>;
hsync-active = <0>;
vsync-active = <0>;
port {
panel_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
......@@ -725,6 +705,12 @@ &lcdc {
status = "okay";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&panel_0>;
};
};
};
&rtc {
......
arch/arm/boot/dts/am335x-icev2.dts
View file @ 1afa9c3b
......@@ -287,6 +287,19 @@ pca9536: gpio@41 {
gpio-controller;
#gpio-cells = <2>;
};
/* osd9616p0899-10 */
display@3c {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
solomon,height = <16>;
solomon,width = <96>;
solomon,com-seq;
solomon,com-invdir;
solomon,page-offset = <0>;
solomon,prechargep1 = <2>;
solomon,prechargep2 = <13>;
};
};
&spi0 {
......
arch/arm/boot/dts/am33xx-l4.dtsi
View file @ 1afa9c3b
......@@ -225,7 +225,6 @@ i2c0: i2c@0 {
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
......@@ -1009,7 +1008,6 @@ i2c1: i2c@0 {
target-module@30000 { /* 0x48030000, ap 77 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
......@@ -1134,7 +1132,6 @@ timer2: timer@0 {
target-module@42000 { /* 0x48042000, ap 24 1c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
......@@ -1160,7 +1157,6 @@ timer3: timer@0 {
target-module@44000 { /* 0x48044000, ap 26 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
......@@ -1187,7 +1183,6 @@ timer4: timer@0 {
target-module@46000 { /* 0x48046000, ap 28 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
......@@ -1214,7 +1209,6 @@ timer5: timer@0 {
target-module@48000 { /* 0x48048000, ap 30 22.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
......@@ -1241,7 +1235,6 @@ timer6: timer@0 {
target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
......@@ -1344,7 +1337,6 @@ mmc1: mmc@0 {
target-module@80000 { /* 0x48080000, ap 38 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
......@@ -1412,7 +1404,6 @@ mbox_wkupm3: wkup_m3 {
target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
......@@ -1533,7 +1524,6 @@ i2c2: i2c@0 {
target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
......@@ -1749,7 +1739,6 @@ target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
......@@ -1773,7 +1762,6 @@ target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
......@@ -1863,7 +1851,6 @@ segment@300000 { /* 0x48300000 */
target-module@0 { /* 0x48300000, ap 66 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
......@@ -1916,7 +1903,6 @@ ehrpwm0: pwm@200 {
target-module@2000 { /* 0x48302000, ap 68 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
......@@ -1969,7 +1955,6 @@ ehrpwm1: pwm@200 {
target-module@4000 { /* 0x48304000, ap 70 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
......@@ -2022,7 +2007,6 @@ ehrpwm2: pwm@200 {
target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "lcdc";
reg = <0xe000 0x4>,
<0xe054 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/am33xx.dtsi
View file @ 1afa9c3b
......@@ -439,23 +439,62 @@ gpmc: gpmc@50000000 {
status = "disabled";
};
sham: sham@53100000 {
compatible = "ti,omap4-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
};
};
aes: aes@53500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53500000 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53500080 0x4>,
<0x53500084 0x4>,
<0x53500088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53500000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
};
};
......
arch/arm/boot/dts/am3517.dtsi
View file @ 1afa9c3b
......@@ -74,7 +74,7 @@ davinci_emac: ethernet@5c000000 {
clock-names = "ick";
};
davinci_mdio: ethernet@5c030000 {
davinci_mdio: mdio@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
......
arch/arm/boot/dts/am3703.dtsi 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
*/
#include "omap36xx.dtsi"
&iva {
status = "disabled";
};
&sgx_module {
status = "disabled";
};
arch/arm/boot/dts/am3715.dtsi 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
*/
#include "omap36xx.dtsi"
&iva {
status = "disabled";
};
arch/arm/boot/dts/am4372.dtsi
View file @ 1afa9c3b
......@@ -256,33 +256,92 @@ mmc3: mmc@0 {
};
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap5-sham";
reg = <0 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
};
aes: aes@53501000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53501000 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53501080 0x4>,
<0x53501084 0x4>,
<0x53501088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53501000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
des: des@53701000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x53701000 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
des_target: target-module@53701000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53701030 0x4>,
<0x53701034 0x4>,
<0x53701038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x53701000 0x1000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
};
};
gpmc: gpmc@50000000 {
......@@ -305,17 +364,34 @@ gpmc: gpmc@50000000 {
status = "disabled";
};
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
target-module@47900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x47900000 0x4>,
<0x47900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
interrupts = <0 138 0x4>;
num-cs = <4>;
status = "disabled";
#size-cells = <1>;
ranges = <0x0 0x47900000 0x1000>,
<0x30000000 0x30000000 0x4000000>;
qspi: spi@0 {
compatible = "ti,am4372-qspi";
reg = <0 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
clocks = <&dpll_per_m2_div4_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 138 0x4>;
num-cs = <4>;
};
};
dss: dss@4832a000 {
......
arch/arm/boot/dts/am437x-l4.dtsi
View file @ 1afa9c3b
......@@ -225,7 +225,6 @@ i2c0: i2c@0 {
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
......@@ -763,7 +762,6 @@ i2c1: i2c@0 {
target-module@30000 { /* 0x48030000, ap 65 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
......@@ -900,7 +898,6 @@ timer2: timer@0 {
target-module@42000 { /* 0x48042000, ap 20 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
......@@ -927,7 +924,6 @@ timer3: timer@0 {
target-module@44000 { /* 0x48044000, ap 22 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
......@@ -955,7 +951,6 @@ timer4: timer@0 {
target-module@46000 { /* 0x48046000, ap 24 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
......@@ -983,7 +978,6 @@ timer5: timer@0 {
target-module@48000 { /* 0x48048000, ap 26 1a.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
......@@ -1011,7 +1005,6 @@ timer6: timer@0 {
target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
......@@ -1107,7 +1100,6 @@ mmc1: mmc@0 {
target-module@80000 { /* 0x48080000, ap 32 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
......@@ -1169,7 +1161,6 @@ mbox_wkupm3: wkup_m3 {
target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
......@@ -1282,7 +1273,6 @@ i2c2: i2c@0 {
target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
......@@ -1313,7 +1303,6 @@ spi1: spi@0 {
target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi2";
reg = <0xa2000 0x4>,
<0xa2110 0x4>,
<0xa2114 0x4>;
......@@ -1344,7 +1333,6 @@ spi2: spi@0 {
target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi3";
reg = <0xa4000 0x4>,
<0xa4110 0x4>,
<0xa4114 0x4>;
......@@ -1527,7 +1515,6 @@ gpio3: gpio@0 {
target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0xc1000 0x4>,
<0xc1010 0x4>,
<0xc1014 0x4>;
......@@ -1556,7 +1543,6 @@ target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
......@@ -1577,7 +1563,6 @@ target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
......@@ -1695,7 +1680,6 @@ segment@300000 { /* 0x48300000 */
target-module@0 { /* 0x48300000, ap 56 40.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
......@@ -1748,7 +1732,6 @@ ehrpwm0: pwm@200 {
target-module@2000 { /* 0x48302000, ap 58 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
......@@ -1801,7 +1784,6 @@ ehrpwm1: pwm@200 {
target-module@4000 { /* 0x48304000, ap 60 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
......@@ -1854,7 +1836,6 @@ ehrpwm2: pwm@200 {
target-module@6000 { /* 0x48306000, ap 96 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss3";
reg = <0x6000 0x4>,
<0x6004 0x4>;
reg-names = "rev", "sysc";
......@@ -1896,7 +1877,6 @@ ehrpwm3: pwm@200 {
target-module@8000 { /* 0x48308000, ap 98 54.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss4";
reg = <0x8000 0x4>,
<0x8004 0x4>;
reg-names = "rev", "sysc";
......@@ -1938,7 +1918,6 @@ ehrpwm4: pwm@48308200 {
target-module@a000 { /* 0x4830a000, ap 100 60.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss5";
reg = <0xa000 0x4>,
<0xa004 0x4>;
reg-names = "rev", "sysc";
......@@ -2086,7 +2065,6 @@ gpio5: gpio@0 {
target-module@26000 { /* 0x48326000, ap 86 66.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe0";
reg = <0x26000 0x4>,
<0x26104 0x4>;
reg-names = "rev", "sysc";
......@@ -2113,7 +2091,6 @@ vpfe0: vpfe@0 {
target-module@28000 { /* 0x48328000, ap 75 0e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe1";
reg = <0x28000 0x4>,
<0x28104 0x4>;
reg-names = "rev", "sysc";
......@@ -2162,7 +2139,6 @@ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3d000 0x4>,
<0x3d010 0x4>,
<0x3d014 0x4>;
......@@ -2189,7 +2165,6 @@ timer9: timer@0 {
target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x3f000 0x4>,
<0x3f010 0x4>,
<0x3f014 0x4>;
......@@ -2216,7 +2191,6 @@ timer10: timer@0 {
target-module@41000 { /* 0x48341000, ap 106 76.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x41000 0x4>,
<0x41010 0x4>,
<0x41014 0x4>;
......@@ -2243,7 +2217,6 @@ timer11: timer@0 {
target-module@45000 { /* 0x48345000, ap 108 6a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi4";
reg = <0x45000 0x4>,
<0x45110 0x4>,
<0x45114 0x4>;
......@@ -2358,7 +2331,6 @@ usb1: usb@10000 {
target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp0";
reg = <0xa8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
......@@ -2440,7 +2412,6 @@ usb2: usb@10000 {
target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp1";
reg = <0xe8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
......
arch/arm/boot/dts/am57xx-idk-common.dtsi
View file @ 1afa9c3b
......@@ -9,6 +9,7 @@ / {
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
display0 = &hdmi0;
};
chosen {
......@@ -96,6 +97,48 @@ led-out7 {
default-state = "off";
};
};
hdmi0: connector@0 {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder@0 {
compatible = "ti,tpd12s016", "ti,tpd12s015";
gpios = <0>, /* optional CT_CP_HPD */
<0>, /* optional LS_OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint@0 {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint@0 {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&dra7_pmx_core {
......@@ -485,3 +528,19 @@ partition@6 {
&cpu0 {
vdd-supply = <&smps12_reg>;
};
&hdmi {
status = "okay";
vdda-supply = <&ldo4_reg>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&dss {
status = "okay";
};
arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "armada-385-clearfog-gtr.dtsi"
/ {
model = "SolidRun Clearfog GTR L8";
};
&mdio {
switch0: switch0@4 {
compatible = "marvell,mv88e6190";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan8";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan7";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan6";
phy-handle = <&switch0phy2>;
};
port@4 {
reg = <4>;
label = "lan5";
phy-handle = <&switch0phy3>;
};
port@5 {
reg = <5>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
port@6 {
reg = <6>;
label = "lan3";
phy-handle = <&switch0phy5>;
};
port@7 {
reg = <7>;
label = "lan2";
phy-handle = <&switch0phy6>;
};
port@8 {
reg = <8>;
label = "lan1";
phy-handle = <&switch0phy7>;
};
port@10 {
reg = <10>;
label = "cpu";
ethernet = <&eth1>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@1 {
reg = <0x1>;
};
switch0phy1: switch0phy1@2 {
reg = <0x2>;
};
switch0phy2: switch0phy2@3 {
reg = <0x3>;
};
switch0phy3: switch0phy3@4 {
reg = <0x4>;
};
switch0phy4: switch0phy4@5 {
reg = <0x5>;
};
switch0phy5: switch0phy5@6 {
reg = <0x6>;
};
switch0phy6: switch0phy6@7 {
reg = <0x7>;
};
switch0phy7: switch0phy7@8 {
reg = <0x8>;
};
};
};
};
arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "armada-385-clearfog-gtr.dtsi"
/ {
model = "SolidRun Clearfog GTR S4";
};
&sfp0 {
tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
&mdio {
switch0: switch0@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&eth1>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
};
};
arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
*
* Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
*/
/*
SERDES mapping -
0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
1. 6141 switch (2.5Gbps capable)
2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
3. USB 3.0 Host
4. mini PCIe CON2 - PCIe2
5. SFP connector, or optionally SGMII Ethernet 1512 PHY
USB 2.0 mapping -
0. USB 2.0 - 0 USB pins header CON12
1. USB 2.0 - 1 mini PCIe CON2
2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
Pin mapping -
0,1 - console UART
2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
front panel and PSE controller
4,5 - MDC/MDIO
6..17 - RGMII
18 - Topaz switch reset (active low)
19 - 1512 phy reset
20 - 1512 phy reset (eth2, optional)
21,28,37,38,39,40 - SD0
22 - USB 3.0 current limiter enable (active high)
24 - SFP TX fault (input active high)
25 - SFP present (input active low)
26,27 - I2C1 - connected to SFP
29 - Fan PWM
30 - CON4 mini PCIe wifi disable
31 - CON3 mini PCIe wifi disable
32 - Fuse programming power toggle (1.8v)
33 - CON4 mini PCIe reset
34 - CON2 mini PCIe wifi disable
35 - CON3 mini PCIe reset
36 - Rear button (GPIO active low)
41 - CON1 front panel connector
42 - Front LED1, or front panel CON1
43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
44 - CON2 mini PCIe reset
45 - TPM PIRQ signal, or front panel CON1
46 - SFP TX disable
47 - Control isolation of boot sensitive SAR signals
48 - PSE reset
49 - PSE OSS signal
50 - PSE interrupt
52 - Front LED2, or front panel
53 - Front button
54 - SFP LOS (input active high)
55 - Fan sense
56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"
/ {
compatible = "marvell,armada385", "marvell,armada380";
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
ethernet2 = &eth1;
ethernet3 = &eth2;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
v_usb3_con: regulator-v-usb3-con {
compatible = "regulator-fixed";
gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "v_usb3_con";
vin-supply = <&reg_5p0v>;
regulator-boot-on;
regulator-always-on;
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
rtc@a3800 {
status = "okay";
};
i2c@11000 { /* ROM, temp sensor and front panel */
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
};
i2c@11100 { /* SFP (CON5/CON6) */
pinctrl-0 = <&cf_gtr_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
pinctrl@18000 {
cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
};
cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
marvell,pins = "mpp22";
marvell,function = "gpio";
};
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
cf_gtr_i2c1_pins: i2c1-pins {
/* SFP */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cf_gtr_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
marvell,pins = "mpp36";
marvell,function = "gpio";
};
};
sdhci@d8000 {
bus-width = <4>;
no-1-8-v;
non-removable;
pinctrl-0 = <&cf_gtr_sdhci_pins>;
pinctrl-names = "default";
status = "okay";
vmmc = <&reg_3p3v>;
wp-inverted;
};
usb@58000 {
status = "okay";
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
vbus-supply = <&v_usb3_con>;
status = "okay";
};
};
pcie {
status = "okay";
/*
* The PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
pcie@1,0 {
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@2,0 {
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@3,0 {
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
};
sfp0: sfp {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
pinctrl-names = "default";
button_0 {
label = "Rear Button";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
button_1 {
label = "Front Button";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_1>;
};
};
gpio-leds {
compatible = "gpio-leds";
led1 {
function = LED_FUNCTION_CPU;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
led2 {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
};
};
};
&bm {
status = "okay";
};
&bm_bppi {
status = "okay";
};
&eth0 {
/* ethernet@70000 */
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy_dedicated>;
phy-mode = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <1>;
status = "okay";
};
&eth1 {
/* ethernet@30000 */
bm,pool-long = <2>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
phys = <&comphy1 1>;
phy-mode = "2500base-x";
status = "okay";
fixed-link {
speed = <2500>;
full-duplex;
};
};
&eth2 {
/* ethernet@34000 */
bm,pool-long = <3>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
managed = "in-band-status";
phys = <&comphy5 1>;
phy-mode = "sgmii";
sfp = <&sfp0>;
status = "okay";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
phy_dedicated: ethernet-phy@0 {
/*
* Annoyingly, the marvell phy driver configures the LED
* register, rather than preserving reset-loaded setting.
* We undo that rubbish here.
*/
marvell,reg-init = <3 16 0 0x1017>;
reg = <0>;
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
/*
* CS0: W25Q32 flash
*/
pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
pinctrl-names = "default";
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "okay";
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/* U26 temperature sensor placed near SoC */
temp1: nct75@4c {
compatible = "lm75";
reg = <0x4c>;
};
/* U27 temperature sensor placed near RTC battery */
temp2: nct75@4d {
compatible = "lm75";
reg = <0x4d>;
};
/* 2Kb eeprom */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
};
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};
&gpio0 {
pinctrl-0 = <&cf_gtr_fan_pwm>;
pinctrl-names = "default";
wifi-disable {
gpio-hog;
gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
output-low;
line-name = "wifi-disable";
};
};
&gpio1 {
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
pinctrl-names = "default";
lte-disable {
gpio-hog;
gpios = <2 GPIO_ACTIVE_LOW>;
output-low;
line-name = "lte-disable";
};
/*
* This signal, when asserted, isolates Armada 38x sample at reset pins
* from control of external devices. Should be de-asserted after reset.
*/
sar-isolation {
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
output-low;
line-name = "sar-isolation";
};
poe-reset {
gpio-hog;
gpios = <16 GPIO_ACTIVE_LOW>;
output-low;
line-name = "poe-reset";
};
};
arch/arm/boot/dts/armada-388-clearfog.dtsi
View file @ 1afa9c3b
......@@ -111,11 +111,6 @@ &eth2 {
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
......@@ -183,6 +178,12 @@ mikrobus_adc: mcp3021@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
};
&i2c1 {
......
arch/arm/boot/dts/armada-388-helios4.dts
View file @ 1afa9c3b
......@@ -140,11 +140,6 @@ usb3_phy: usb3-phy {
soc {
internal-regs {
i2c@11000 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-Board Revision bit 0 #
......
arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
View file @ 1afa9c3b
......@@ -71,6 +71,19 @@ phy_dedicated: ethernet-phy@0 {
};
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&pinctrl {
microsom_phy_clk_pins: microsom-phy-clk-pins {
marvell,pins = "mpp45";
......
arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
View file @ 1afa9c3b
......@@ -76,7 +76,6 @@ &uart5 {
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
......
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
View file @ 1afa9c3b
......@@ -75,7 +75,6 @@ &uart5 {
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
......
arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
View file @ 1afa9c3b
......@@ -35,7 +35,6 @@ &uart2 {
&mac0 {
status = "okay";
use-ncsi;
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
......
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
View file @ 1afa9c3b
......@@ -97,22 +97,22 @@ &i2c3 {
status = "okay";
power-supply@68 {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x68>;
};
power-supply@69 {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x69>;
};
power-supply@6a {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x6b>;
};
};
......@@ -352,18 +352,8 @@ eeprom@51 {
&i2c8 {
status = "okay";
ucd90320@b {
compatible = "ti,ucd90160";
reg = <0x0b>;
};
ucd90320@c {
compatible = "ti,ucd90160";
reg = <0x0c>;
};
ucd90320@11 {
compatible = "ti,ucd90160";
compatible = "ti,ucd90320";
reg = <0x11>;
};
......
arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
View file @ 1afa9c3b
......@@ -94,8 +94,6 @@ ps1-presence {
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
......
arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
View file @ 1afa9c3b
......@@ -82,8 +82,6 @@ iio-hwmon-battery {
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
scm0-presence {
......
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
View file @ 1afa9c3b
......@@ -14,7 +14,7 @@ chosen {
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
......@@ -107,10 +107,7 @@ flash@0 {
&mac0 {
status = "okay";
use-ncsi;
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
......@@ -236,3 +233,16 @@ &vuart {
&wdt2 {
aspeed,alt-boot;
};
&sdmmc {
status = "okay";
};
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
cd-inverted;
disable-wp;
};
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
View file @ 1afa9c3b
......@@ -77,8 +77,6 @@ iio-hwmon-battery {
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
......
arch/arm/boot/dts/aspeed-g4.dtsi
View file @ 1afa9c3b
......@@ -179,18 +179,21 @@ syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2400-pinctrl";
};
p2a: p2a-control {
p2a: p2a-control@2c {
reg = <0x2c 0x4>;
compatible = "aspeed,ast2400-p2a-ctrl";
status = "disabled";
};
pinctrl: pinctrl@80 {
reg = <0x80 0x18>, <0xa0 0x10>;
compatible = "aspeed,ast2400-pinctrl";
};
};
rng: hwrng@1e6e2078 {
......@@ -346,14 +349,14 @@ lpc_host: lpc-host@80 {
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
reg = <0x0 0x80>;
reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2400-lpc-snoop";
reg = <0x0 0x80>;
reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};
......
arch/arm/boot/dts/aspeed-g5.dtsi
View file @ 1afa9c3b
......@@ -47,13 +47,6 @@ memory@80000000 {
reg = <0x80000000 0>;
};
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2500-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <0>;
status = "disabled";
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -213,24 +206,33 @@ apb {
#size-cells = <1>;
ranges;
edac: memory-controller@1e6e0000 {
compatible = "aspeed,ast2500-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <0>;
status = "disabled";
};
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
p2a: p2a-control {
p2a: p2a-control@2c {
compatible = "aspeed,ast2500-p2a-ctrl";
reg = <0x2c 0x4>;
status = "disabled";
};
pinctrl: pinctrl@80 {
compatible = "aspeed,ast2500-pinctrl";
reg = <0x80 0x18>, <0xa0 0x10>;
aspeed,external-nodes = <&gfx>, <&lhc>;
};
};
rng: hwrng@1e6e2078 {
......@@ -460,29 +462,30 @@ kcs4: kcs4@0 {
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2500-lpc-snoop";
reg = <0x0 0x80>;
reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
ibt: ibt@c0 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;
......
arch/arm/boot/dts/aspeed-g6.dtsi
View file @ 1afa9c3b
......@@ -365,7 +365,7 @@ wdt3: watchdog@1e785080 {
status = "disabled";
};
wdt4: watchdog@1e7850C0 {
wdt4: watchdog@1e7850c0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";
......
arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi
View file @ 1afa9c3b
......@@ -71,7 +71,6 @@ flash1@0 {
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
......
arch/arm/boot/dts/at91-kizbox.dts
View file @ 1afa9c3b
......@@ -28,85 +28,6 @@ main_xtal {
};
};
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
usart3: serial@fffd0000 {
status = "okay";
};
dbgu: serial@fffff200 {
status = "okay";
};
watchdog@fffffd40 {
timeout-sec = <15>;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
status = "okay";
};
};
usb0: ohci@500000 {
num-ports = <1>;
status = "okay";
};
ebi: ebi@10000000 {
status = "okay";
nand_controller: nand-controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
......@@ -127,15 +48,6 @@ user {
};
};
i2c-gpio-0 {
status = "okay";
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
pwm_leds {
compatible = "pwm-leds";
......@@ -179,3 +91,87 @@ &pinctrl_tcb1_tioa2
&pinctrl_tcb1_tiob0>;
};
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
&ebi {
status = "okay";
};
&nand_controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
&macb0 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
&usart3 {
status = "okay";
};
&dbgu {
status = "okay";
};
&watchdog {
timeout-sec = <15>;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
status = "okay";
};
&usb0 {
num-ports = <1>;
status = "okay";
};
&i2c_gpio0 {
status = "okay";
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
arch/arm/boot/dts/at91-kizboxmini-base.dts 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini
* base board
*
* Copyright (C) 2015 Overkiz SAS
* Author: Antoine Aubert <a.aubert@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini";
compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
};
&pinctrl_usart0 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
};
arch/arm/boot/dts/at91-kizboxmini.dts → arch/arm/boot/dts/at91-kizboxmini-common.dtsi
View file @ 1afa9c3b
// SPDX-License-Identifier: GPL-2.0-or-later
// SPDX-License-Identifier: GPL-2.0
/*
* at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
*
* Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
* Copyright (C) 2014-2018 Overkiz SAS
* Author: Antoine Aubert <a.aubert@overkiz.com>
* Gaël Portay <g.portay@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
* Dorian Rocipon <d.rocipon@overkiz.com>
*/
/dts-v1/;
#include "at91sam9g25.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Overkiz Kizbox mini";
compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
bootargs = "ubi.mtd=ubi";
stdout-path = &dbgu;
......@@ -22,24 +21,16 @@ memory {
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
slow_xtal {
clock-frequency = <32768>;
};
adc_op_clk {
status = "disabled";
};
};
......@@ -63,17 +54,25 @@ reset {
};
};
pwm_leds {
leds: pwm_leds {
compatible = "pwm-leds";
green {
led_blue: pwm_blue {
label = "pwm:blue:user";
pwms = <&pwm0 2 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "none";
status = "disabled";
};
led_green: pwm_green {
label = "pwm:green:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
red {
led_red: pwm_red {
label = "pwm:red:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
......@@ -82,53 +81,12 @@ red {
};
};
&dbgu {
&usart0 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
nand-controller {
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
&macb0 {
phy-mode = "rmii";
status = "okay";
......@@ -137,26 +95,70 @@ &macb0 {
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1
&pinctrl_pwm0_pwm1_1>;
&pinctrl_pwm0_pwm1_1
&pinctrl_pwm0_pwm2_1>;
status = "okay";
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
&dbgu {
status = "okay";
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
&watchdog {
status = "okay";
};
&usart0 {
&adc0 {
status = "disabled";
};
&rtc {
status = "disabled";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
};
&nand_controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
&usb0 {
num-ports = <1>;
status = "okay";
......@@ -166,6 +168,3 @@ &usb1 {
status = "okay";
};
&watchdog {
status = "okay";
};
arch/arm/boot/dts/at91-kizboxmini-mb.dts 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2018 Overkiz SAS
* Author: Mickael Gardet <m.gardet@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini Mother Board";
compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
};
&usb0 {
num-ports = <2>;
};
&rtc {
status = "okay";
};
&led_blue {
status = "okay";
};
arch/arm/boot/dts/at91-kizboxmini-rd.dts 0 → 100644
View file @ 1afa9c3b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2018 Overkiz SAS
* Author: Mickael Gardet <m.gardet@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini RailDIN";
compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
clocks {
adc_op_clk {
status = "okay";
};
};
};
&pinctrl {
adc0 {
pinctrl_adc0_ad5: adc0_ad5-0 {
/* pull-up disable */
atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
&usart0 {
status = "disabled";
};
&rtc {
status = "okay";
};
&led_blue {
status = "okay";
};
&adc0 {
atmel,adc-vref = <2500>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_ad5>;
atmel,adc-channels-used = <0x0020>;
status = "okay";
};
arch/arm/boot/dts/at91-nattis-2-natte-2.dts
View file @ 1afa9c3b
......@@ -8,7 +8,6 @@
*/
/dts-v1/;
#include "at91-linea.dtsi"
#include "sama5d3_lcd.dtsi"
#include "at91-natte.dtsi"
/ {
......
arch/arm/boot/dts/at91-sam9x60ek.dts 0 → 100644
View file @ 1afa9c3b
This diff is collapsed.
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
View file @ 1afa9c3b
......@@ -24,6 +24,10 @@ main_xtal {
};
ahb {
sdmmc0: sdio-host@a0000000 {
microchip,sdcal-inverted;
};
apb {
qspi1: spi@f0024000 {
pinctrl-names = "default";
......
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View file @ 1afa9c3b
......@@ -131,6 +131,9 @@ i2c2: i2c@600 {
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
......@@ -246,6 +249,9 @@ i2c3: i2c@600 {
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
......
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