Commit 1c425915 authored by Shirish S's avatar Shirish S Committed by Alex Deucher

drm/amd/display: enable S/G for RAVEN chip

enables gpu_vm_support in dm and adds
AMDGPU_GEM_DOMAIN_GTT as supported domain

v2:
Move BO placement logic into amdgpu_display_supported_domains

v3:
Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.

v4:
amdgpu_bo_validate_uswc moved to sepperate patch.
Signed-off-by: default avatarShirish S <shirish.s@amd.com>
Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ddcb7fc6
...@@ -507,7 +507,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) ...@@ -507,7 +507,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
* APUs. So force the BO placement to VRAM in case this architecture * APUs. So force the BO placement to VRAM in case this architecture
* will not allow USWC mappings. * will not allow USWC mappings.
*/ */
if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) && adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) &&
amdgpu_device_asic_has_dc_support(adev->asic_type)) amdgpu_device_asic_has_dc_support(adev->asic_type))
domain |= AMDGPU_GEM_DOMAIN_GTT; domain |= AMDGPU_GEM_DOMAIN_GTT;
......
...@@ -688,7 +688,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) ...@@ -688,7 +688,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
*/ */
if (adev->flags & AMD_IS_APU && if (adev->flags & AMD_IS_APU &&
adev->asic_type >= CHIP_CARRIZO && adev->asic_type >= CHIP_CARRIZO &&
adev->asic_type < CHIP_RAVEN) adev->asic_type <= CHIP_RAVEN)
init_data.flags.gpu_vm_support = true; init_data.flags.gpu_vm_support = true;
if (amdgpu_dc_feature_mask & DC_FBC_MASK) if (amdgpu_dc_feature_mask & DC_FBC_MASK)
......
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