Commit 1c8b4df7 authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo

ARM: dts: imx7-mba7: Add SPI1_SS0 as chip select 3

ECSPI1.SS0 was missing in the list.
Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 123098a1
...@@ -209,9 +209,9 @@ &adc2 { ...@@ -209,9 +209,9 @@ &adc2 {
&ecspi1 { &ecspi1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>; pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
<&gpio4 2 GPIO_ACTIVE_LOW>; <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
...@@ -357,6 +357,12 @@ pinctrl_ecspi1: ecspi1grp { ...@@ -357,6 +357,12 @@ pinctrl_ecspi1: ecspi1grp {
<MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>; <MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>;
}; };
pinctrl_ecspi1_ss0: ecspi1ss0grp {
fsl,pins = <
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74
>;
};
pinctrl_ecspi2: ecspi2grp { pinctrl_ecspi2: ecspi2grp {
fsl,pins = fsl,pins =
<MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>, <MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>,
......
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