Commit 1d0e622f authored by Kevin Wang's avatar Kevin Wang Committed by Alex Deucher

drm/amd/pm: change pp_dpm_sclk/mclk/fclk attribute is RO for aldebaran

the following clock is only support voltage DPM, change attribute to RO:
1. pp_dpm_sclk
2. pp_dpm_mclk
3. pp_dpm_fclk
Signed-off-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent becf6c95
...@@ -2094,14 +2094,19 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ ...@@ -2094,14 +2094,19 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
*states = ATTR_STATE_UNSUPPORTED; *states = ATTR_STATE_UNSUPPORTED;
} }
if (asic_type == CHIP_ARCTURUS) { switch (asic_type) {
/* Arcturus does not support standalone mclk/socclk/fclk level setting */ case CHIP_ARCTURUS:
case CHIP_ALDEBARAN:
/* the Mi series card does not support standalone mclk/socclk/fclk level setting */
if (DEVICE_ATTR_IS(pp_dpm_mclk) || if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
DEVICE_ATTR_IS(pp_dpm_socclk) || DEVICE_ATTR_IS(pp_dpm_socclk) ||
DEVICE_ATTR_IS(pp_dpm_fclk)) { DEVICE_ATTR_IS(pp_dpm_fclk)) {
dev_attr->attr.mode &= ~S_IWUGO; dev_attr->attr.mode &= ~S_IWUGO;
dev_attr->store = NULL; dev_attr->store = NULL;
} }
break;
default:
break;
} }
if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
......
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