Commit 1f065544 authored by Mugunthan V N's avatar Mugunthan V N Committed by David S. Miller

ARM: dts: dra72-evm-revc: fix correct phy delay

The current delay settings of the phy are not the optimal value,
fix it with correct values.
Signed-off-by: default avatarMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b76db38c
...@@ -59,16 +59,16 @@ &cpsw_emac1 { ...@@ -59,16 +59,16 @@ &cpsw_emac1 {
&davinci_mdio { &davinci_mdio {
dp83867_0: ethernet-phy@2 { dp83867_0: ethernet-phy@2 {
reg = <2>; reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance; ti,min-output-impedance;
}; };
dp83867_1: ethernet-phy@3 { dp83867_1: ethernet-phy@3 {
reg = <3>; reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-imepdance; ti,min-output-imepdance;
}; };
......
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