Commit 1f5d492a authored by David S. Miller's avatar David S. Miller

Merge branch 'ravb-gigabit-R-Car-H3-ES1.1-and-R-Car-M3-W'

Simon Horman says:

====================
ravb: Support 1Gbps on R-Car H3 ES1.1+ and R-Car M3-W

this series adds support for gigabit communication to the Renesas
EthernetAVB controller when used in conjunction with R-Car Gen3 H3
ES1.1+ and M3-W SoCs.  Gigabit is already supported with R-Car Gen 2
SoCs.

The patch from Geert was previously posted for inclusion in v4.10 and
acked by Dave for that purpose. It was, however, not accepted by the
ARM SoC maintainers.

The path from Mizuguchi-san is to address timing problems observed
with gigabit transfers. I would like it considered although my own
testing on M3-W did not show any timing problems.

Changes since v1:
* Address various feedback for "APSR" patch as noted in its changelog
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1a28242b 0e98f9d5
...@@ -76,6 +76,7 @@ enum ravb_reg { ...@@ -76,6 +76,7 @@ enum ravb_reg {
CDAR20 = 0x0060, CDAR20 = 0x0060,
CDAR21 = 0x0064, CDAR21 = 0x0064,
ESR = 0x0088, ESR = 0x0088,
APSR = 0x008C, /* R-Car Gen3 only */
RCR = 0x0090, RCR = 0x0090,
RQC0 = 0x0094, RQC0 = 0x0094,
RQC1 = 0x0098, RQC1 = 0x0098,
...@@ -248,6 +249,15 @@ enum ESR_BIT { ...@@ -248,6 +249,15 @@ enum ESR_BIT {
ESR_EIL = 0x00001000, ESR_EIL = 0x00001000,
}; };
/* APSR */
enum APSR_BIT {
APSR_MEMS = 0x00000002,
APSR_CMSW = 0x00000010,
APSR_DM = 0x00006000, /* Undocumented? */
APSR_DM_RDM = 0x00002000,
APSR_DM_TDM = 0x00004000,
};
/* RCR */ /* RCR */
enum RCR_BIT { enum RCR_BIT {
RCR_EFFS = 0x00000001, RCR_EFFS = 0x00000001,
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/sys_soc.h>
#include <asm/div64.h> #include <asm/div64.h>
...@@ -988,6 +989,11 @@ static void ravb_adjust_link(struct net_device *ndev) ...@@ -988,6 +989,11 @@ static void ravb_adjust_link(struct net_device *ndev)
phy_print_status(phydev); phy_print_status(phydev);
} }
static const struct soc_device_attribute r8a7795es10[] = {
{ .soc_id = "r8a7795", .revision = "ES1.0", },
{ /* sentinel */ }
};
/* PHY init function */ /* PHY init function */
static int ravb_phy_init(struct net_device *ndev) static int ravb_phy_init(struct net_device *ndev)
{ {
...@@ -1023,10 +1029,10 @@ static int ravb_phy_init(struct net_device *ndev) ...@@ -1023,10 +1029,10 @@ static int ravb_phy_init(struct net_device *ndev)
goto err_deregister_fixed_link; goto err_deregister_fixed_link;
} }
/* This driver only support 10/100Mbit speeds on Gen3 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
* at this time. * at this time.
*/ */
if (priv->chip_id == RCAR_GEN3) { if (soc_device_match(r8a7795es10)) {
err = phy_set_max_speed(phydev, SPEED_100); err = phy_set_max_speed(phydev, SPEED_100);
if (err) { if (err) {
netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
...@@ -1920,6 +1926,23 @@ static void ravb_set_config_mode(struct net_device *ndev) ...@@ -1920,6 +1926,23 @@ static void ravb_set_config_mode(struct net_device *ndev)
} }
} }
/* Set tx and rx clock internal delay modes */
static void ravb_set_delay_mode(struct net_device *ndev)
{
struct ravb_private *priv = netdev_priv(ndev);
int set = 0;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
set |= APSR_DM_RDM;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
set |= APSR_DM_TDM;
ravb_modify(ndev, APSR, APSR_DM, set);
}
static int ravb_probe(struct platform_device *pdev) static int ravb_probe(struct platform_device *pdev)
{ {
struct device_node *np = pdev->dev.of_node; struct device_node *np = pdev->dev.of_node;
...@@ -2032,6 +2055,9 @@ static int ravb_probe(struct platform_device *pdev) ...@@ -2032,6 +2055,9 @@ static int ravb_probe(struct platform_device *pdev)
/* Request GTI loading */ /* Request GTI loading */
ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
if (priv->chip_id != RCAR_GEN2)
ravb_set_delay_mode(ndev);
/* Allocate descriptor base address table */ /* Allocate descriptor base address table */
priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
...@@ -2168,6 +2194,9 @@ static int __maybe_unused ravb_resume(struct device *dev) ...@@ -2168,6 +2194,9 @@ static int __maybe_unused ravb_resume(struct device *dev)
/* Request GTI loading */ /* Request GTI loading */
ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
if (priv->chip_id != RCAR_GEN2)
ravb_set_delay_mode(ndev);
/* Restore descriptor base address table */ /* Restore descriptor base address table */
ravb_write(ndev, priv->desc_bat_dma, DBAT); ravb_write(ndev, priv->desc_bat_dma, DBAT);
......
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