net: ethernet: oa_tc6: implement software reset
Reset complete bit is set when the MAC-PHY reset completes and ready for configuration. Additionally reset complete bit in the STS0 register has to be written by one upon reset complete to clear the interrupt. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com> Link: https://patch.msgid.link/20240909082514.262942-5-Parthiban.Veerasooran@microchip.comSigned-off-by: Jakub Kicinski <kuba@kernel.org>
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