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Commit 203734a0 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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pinctrl: renesas: r8a779g0: Fix Group 6/7 pin functions 

According to R-Car V4H Series User’s Manual: Hardware Rev. 0.54, pin
groups 6 and 7 do not use Module Select Registers to configure pin
functions.

Hence:
  - Remove the non-existent Module Select Registers (MODSEL[67]),
  - Correct the affected PINMUX definitions.

Fixes: 36611d28 ("pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBx")
Fixes: ad9bb2fe ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/06972cafd0efa4cfb395cfa76000a1bdae5e9e73.1669036423.git.geert+renesas@glider.be
parent 0a7a5226
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Showing with 49 additions and 122 deletions
drivers/pinctrl/renesas/pfc-r8a779g0.c
View file @ 203734a0
......@@ -649,30 +649,6 @@ FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
FM(IP0SR8_27_24) IP0SR8_27_24 \
FM(IP0SR8_31_28) IP0SR8_31_28
/* MOD_SEL6 */ /* 0 */ /* 1 */
#define MOD_SEL6_18 FM(SEL_AVB1_TD3_0) FM(SEL_AVB1_TD3_1)
#define MOD_SEL6_16 FM(SEL_AVB1_TD2_0) FM(SEL_AVB1_TD2_1)
#define MOD_SEL6_13 FM(SEL_AVB1_TD0_0) FM(SEL_AVB1_TD0_1)
#define MOD_SEL6_12 FM(SEL_AVB1_TD1_0) FM(SEL_AVB1_TD1_1)
#define MOD_SEL6_10 FM(SEL_AVB1_AVTP_PPS_0) FM(SEL_AVB1_AVTP_PPS_1)
#define MOD_SEL6_7 FM(SEL_AVB1_TX_CTL_0) FM(SEL_AVB1_TX_CTL_1)
#define MOD_SEL6_6 FM(SEL_AVB1_TXC_0) FM(SEL_AVB1_TXC_1)
#define MOD_SEL6_5 FM(SEL_AVB1_AVTP_MATCH_0) FM(SEL_AVB1_AVTP_MATCH_1)
#define MOD_SEL6_2 FM(SEL_AVB1_MDC_0) FM(SEL_AVB1_MDC_1)
#define MOD_SEL6_1 FM(SEL_AVB1_MAGIC_0) FM(SEL_AVB1_MAGIC_1)
/* MOD_SEL7 */ /* 0 */ /* 1 */
#define MOD_SEL7_16 FM(SEL_AVB0_TX_CTL_0) FM(SEL_AVB0_TX_CTL_1)
#define MOD_SEL7_15 FM(SEL_AVB0_TXC_0) FM(SEL_AVB0_TXC_1)
#define MOD_SEL7_13 FM(SEL_AVB0_MDC_0) FM(SEL_AVB0_MDC_1)
#define MOD_SEL7_11 FM(SEL_AVB0_TD0_0) FM(SEL_AVB0_TD0_1)
#define MOD_SEL7_10 FM(SEL_AVB0_MAGIC_0) FM(SEL_AVB0_MAGIC_1)
#define MOD_SEL7_7 FM(SEL_AVB0_TD1_0) FM(SEL_AVB0_TD1_1)
#define MOD_SEL7_6 FM(SEL_AVB0_TD2_0) FM(SEL_AVB0_TD2_1)
#define MOD_SEL7_3 FM(SEL_AVB0_TD3_0) FM(SEL_AVB0_TD3_1)
#define MOD_SEL7_2 FM(SEL_AVB0_AVTP_MATCH_0) FM(SEL_AVB0_AVTP_MATCH_1)
#define MOD_SEL7_0 FM(SEL_AVB0_AVTP_PPS_0) FM(SEL_AVB0_AVTP_PPS_1)
/* MOD_SEL8 */ /* 0 */ /* 1 */
#define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
#define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
......@@ -689,23 +665,18 @@ FM(IP0SR8_31_28) IP0SR8_31_28
#define PINMUX_MOD_SELS \
\
MOD_SEL6_18 \
MOD_SEL6_16 MOD_SEL7_16 \
MOD_SEL7_15 \
MOD_SEL6_13 MOD_SEL7_13 \
MOD_SEL6_12 \
MOD_SEL7_11 MOD_SEL8_11 \
MOD_SEL6_10 MOD_SEL7_10 MOD_SEL8_10 \
MOD_SEL8_9 \
MOD_SEL8_8 \
MOD_SEL6_7 MOD_SEL7_7 MOD_SEL8_7 \
MOD_SEL6_6 MOD_SEL7_6 MOD_SEL8_6 \
MOD_SEL6_5 MOD_SEL8_5 \
MOD_SEL8_4 \
MOD_SEL7_3 MOD_SEL8_3 \
MOD_SEL6_2 MOD_SEL7_2 MOD_SEL8_2 \
MOD_SEL6_1 MOD_SEL8_1 \
MOD_SEL7_0 MOD_SEL8_0
MOD_SEL8_11 \
MOD_SEL8_10 \
MOD_SEL8_9 \
MOD_SEL8_8 \
MOD_SEL8_7 \
MOD_SEL8_6 \
MOD_SEL8_5 \
MOD_SEL8_4 \
MOD_SEL8_3 \
MOD_SEL8_2 \
MOD_SEL8_1 \
MOD_SEL8_0
enum {
PINMUX_RESERVED = 0,
......@@ -1092,23 +1063,23 @@ static const u16 pinmux_data[] = {
/* IP0SR6 */
PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
PINMUX_IPSR_MSEL(IP0SR6_7_4, AVB1_MAGIC, SEL_AVB1_MAGIC_1),
PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
PINMUX_IPSR_MSEL(IP0SR6_11_8, AVB1_MDC, SEL_AVB1_MDC_1),
PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_AVTP_MATCH, SEL_AVB1_AVTP_MATCH_1),
PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_MII_RX_ER, SEL_AVB1_AVTP_MATCH_0),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_TXC, SEL_AVB1_TXC_1),
PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_MII_TXC, SEL_AVB1_TXC_0),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_TX_CTL, SEL_AVB1_TX_CTL_1),
PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_MII_TX_EN, SEL_AVB1_TX_CTL_0),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
/* IP1SR6 */
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
......@@ -1117,17 +1088,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_AVTP_PPS, SEL_AVB1_AVTP_PPS_1),
PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_MII_COL, SEL_AVB1_AVTP_PPS_0),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_TD1, SEL_AVB1_TD1_1),
PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_MII_TD1, SEL_AVB1_TD1_0),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_TD0, SEL_AVB1_TD0_1),
PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_MII_TD0, SEL_AVB1_TD0_0),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
......@@ -1136,14 +1107,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
/* IP2SR6 */
PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_TD2, SEL_AVB1_TD2_1),
PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_MII_TD2, SEL_AVB1_TD2_0),
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_TD3, SEL_AVB1_TD3_1),
PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_MII_TD3, SEL_AVB1_TD3_0),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
......@@ -1151,29 +1122,29 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
/* IP0SR7 */
PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_AVTP_PPS, SEL_AVB0_AVTP_PPS_1),
PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_MII_COL, SEL_AVB0_AVTP_PPS_0),
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_AVTP_MATCH, SEL_AVB0_AVTP_MATCH_1),
PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_MII_RX_ER, SEL_AVB0_AVTP_MATCH_0),
PINMUX_IPSR_MSEL(IP0SR7_11_8, CC5_OSCOUT, SEL_AVB0_AVTP_MATCH_0),
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_TD3, SEL_AVB0_TD3_1),
PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_MII_TD3, SEL_AVB0_TD3_0),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_TD2, SEL_AVB0_TD2_1),
PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_MII_TD2, SEL_AVB0_TD2_0),
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_TD1, SEL_AVB0_TD1_1),
PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_MII_TD1, SEL_AVB0_TD1_0),
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
/* IP1SR7 */
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
......@@ -1181,24 +1152,24 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
PINMUX_IPSR_MSEL(IP1SR7_11_8, AVB0_MAGIC, SEL_AVB0_MAGIC_1),
PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_TD0, SEL_AVB0_TD0_1),
PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_MII_TD0, SEL_AVB0_TD0_0),
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
PINMUX_IPSR_MSEL(IP1SR7_23_20, AVB0_MDC, SEL_AVB0_MDC_1),
PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_TXC, SEL_AVB0_TXC_1),
PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_MII_TXC, SEL_AVB0_TXC_0),
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
/* IP2SR7 */
PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_TX_CTL, SEL_AVB0_TX_CTL_1),
PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_MII_TX_EN, SEL_AVB0_TX_CTL_0),
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
......@@ -3693,50 +3664,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
GROUP(-13, 1, -1, 1, -2, 1, 1,
-1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
GROUP(
/* RESERVED 31-19 */
MOD_SEL6_18
/* RESERVED 17 */
MOD_SEL6_16
/* RESERVED 15-14 */
MOD_SEL6_13
MOD_SEL6_12
/* RESERVED 11 */
MOD_SEL6_10
/* RESERVED 9-8 */
MOD_SEL6_7
MOD_SEL6_6
MOD_SEL6_5
/* RESERVED 4-3 */
MOD_SEL6_2
MOD_SEL6_1
/* RESERVED 0 */
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
-2, 1, 1, -1, 1),
GROUP(
/* RESERVED 31-17 */
MOD_SEL7_16
MOD_SEL7_15
/* RESERVED 14 */
MOD_SEL7_13
/* RESERVED 12 */
MOD_SEL7_11
MOD_SEL7_10
/* RESERVED 9-8 */
MOD_SEL7_7
MOD_SEL7_6
/* RESERVED 5-4 */
MOD_SEL7_3
MOD_SEL7_2
/* RESERVED 1 */
MOD_SEL7_0))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
......
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