Commit 21da5332 authored by Matt Redfearn's avatar Matt Redfearn Committed by Ralf Baechle

MIPS: Introduce cpu_tcache_line_size

There exist macros to return the cache line size of the L1 dcache and L2
scache but there is currently no macro for the L3 tcache. Add this macro
which will be used by the following patch "MIPS: PCI: Fix
smp_processor_id() in preemptible"
Signed-off-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16871/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 68fe5568
...@@ -428,6 +428,9 @@ ...@@ -428,6 +428,9 @@
#ifndef cpu_scache_line_size #ifndef cpu_scache_line_size
#define cpu_scache_line_size() cpu_data[0].scache.linesz #define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif #endif
#ifndef cpu_tcache_line_size
#define cpu_tcache_line_size() cpu_data[0].tcache.linesz
#endif
#ifndef cpu_hwrena_impl_bits #ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits 0 #define cpu_hwrena_impl_bits 0
......
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