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Commit 226fe7c1 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'v4.12-next-dts32' of https://github.com/mbgg/linux-mediatek into next/dt 

Add device tree nodes for
mt7623:
- clocks
- power domain
- pmic-wrapper
- pinctrl
- i2c
- spi
- nand
- mmc
- usb
- pwm
- ethernet
- crypto engine
- infared remote control
- audio controller
- ADC
- efuse
- thermal driver
- HW random generator

mt2701:
- NOR flash
- JPEG decoder
- i2c
- audio controller

* tag 'v4.12-next-dts32' of https://github.com/mbgg/linux-mediatek: (25 commits)
  arm: dts: mediatek: Add audio driver node for MT2701
  arm: dts: Add Mediatek MT2701 i2c device node
  arm: dts: mt2701: Add node for Mediatek JPEG Decoder
  arm: dts: mt2701: add nor flash node
  ARM: dts: mt2701: Add mtk-cirq node for mt2701
  arm: dts: mt7623: add Sean as one of authors for mt7623.dtsi files
  arm: dts: mt7623: add thermal nodes to the mt7623.dtsi file
  arm: dts: mt7623: add efuse nodes to the mt7623.dtsi file
  arm: dts: mt7623: add auxadc nodes to the mt7623.dtsi file
  arm: dts: mt7623: add rng nodes to the mt7623.dtsi file
  arm: dts: mt7623: add afe nodes to the mt7623.dtsi file
  arm: dts: mt7623: add ir nodes to the mt7623.dtsi file
  arm: dts: mt7623: add crypto engine nodes to the mt7623.dtsi file
  arm: dts: mt7623: add ethernet nodes to the mt7623.dtsi file
  arm: dts: mt7623: add pwm nodes to the mt7623.dtsi file
  arm: dts: mt7623: add usb nodes to the mt7623.dtsi file
  arm: dts: mt7623: add mmc nodes to the mt7623.dtsi file
  arm: dts: mt7623: add nand nodes to the mt7623.dtsi file
  arm: dts: mt7623: add spi nodes to the mt7623.dtsi file
  arm: dts: mt7623: add i2c nodes to the mt7623.dtsi file
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3a1fc4d2 aac5e972
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Showing with 846 additions and 11 deletions
arch/arm/boot/dts/mt2701-evb.dts
View file @ 226fe7c1
......@@ -22,13 +22,95 @@ / {
memory {
reg = <0 0x80000000 0 0x40000000>;
};
sound:sound {
compatible = "mediatek,mt2701-cs42448-machine";
mediatek,platform = <&afe>;
/* CS42448 Machine name */
audio-routing =
"Line Out Jack", "AOUT1L",
"Line Out Jack", "AOUT1R",
"Line Out Jack", "AOUT2L",
"Line Out Jack", "AOUT2R",
"Line Out Jack", "AOUT3L",
"Line Out Jack", "AOUT3R",
"Line Out Jack", "AOUT4L",
"Line Out Jack", "AOUT4R",
"AIN1L", "AMIC",
"AIN1R", "AMIC",
"AIN2L", "Tuner In",
"AIN2R", "Tuner In",
"AIN3L", "Satellite Tuner In",
"AIN3R", "Satellite Tuner In",
"AIN3L", "AUX In",
"AIN3R", "AUX In";
mediatek,audio-codec = <&cs42448>;
mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
i2s1-in-sel-gpio1 = <&pio 53 0>;
i2s1-in-sel-gpio2 = <&pio 54 0>;
status = "okay";
};
bt_sco_codec:bt_sco_codec {
compatible = "linux,bt-sco";
};
};
&auxadc {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
cs42448: cs42448@48 {
compatible = "cirrus,cs42448";
reg = <0x48>;
clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>;
clock-names = "mclk";
};
};
&pio {
i2c0_pins_a: i2c0@0 {
pins1 {
pinmux = <MT2701_PIN_75_SDA0__FUNC_SDA0>,
<MT2701_PIN_76_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1@0 {
pins1 {
pinmux = <MT2701_PIN_57_SDA1__FUNC_SDA1>,
<MT2701_PIN_58_SCL1__FUNC_SCL1>;
bias-disable;
};
};
i2c2_pins_a: i2c2@0 {
pins1 {
pinmux = <MT2701_PIN_77_SDA2__FUNC_SDA2>,
<MT2701_PIN_78_SCL2__FUNC_SCL2>;
bias-disable;
};
};
spi_pins_a: spi0@0 {
pins_spi {
pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
......@@ -39,6 +121,31 @@ pins_spi {
};
};
aud_pins_default: audiodefault {
pins_cmd_dat {
pinmux = <MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA>,
<MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN>,
<MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK>,
<MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK>,
<MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK>,
<MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA>,
<MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN>,
<MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK>,
<MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK>,
<MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK>,
<MT2701_PIN_203_PWM0__FUNC_I2S2_DATA>,
<MT2701_PIN_204_PWM1__FUNC_I2S3_DATA>,
<MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53>,
<MT2701_PIN_54_SPI0_CK__FUNC_GPIO54>,
<MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK>,
<MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC>,
<MT2701_PIN_20_PCM_RX__FUNC_MRG_TX>,
<MT2701_PIN_21_PCM_TX__FUNC_MRG_RX>;
drive-strength = <MTK_DRIVE_12mA>;
bias-pull-down;
};
};
spi_pins_b: spi1@0 {
pins_spi {
pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
......@@ -78,6 +185,31 @@ &spi2 {
status = "disabled";
};
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&nor_pins_default>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
&pio {
nor_pins_default: nor {
pins1 {
pinmux = <MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS>,
<MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK>,
<MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0>,
<MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>,
<MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>,
<MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up;
};
};
};
&uart0 {
status = "okay";
};
arch/arm/boot/dts/mt2701.dtsi
View file @ 226fe7c1
......@@ -16,13 +16,14 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
/ {
compatible = "mediatek,mt2701";
interrupt-parent = <&sysirq>;
interrupt-parent = <&cirq>;
cpus {
#address-cells = <1>;
......@@ -210,6 +211,16 @@ sysirq: interrupt-controller@10200100 {
reg = <0 0x10200100 0 0x1c>;
};
cirq: interrupt-controller@10204000 {
compatible = "mediatek,mt2701-cirq",
"mediatek,mtk-cirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&sysirq>;
reg = <0 0x10204000 0 0x400>;
mediatek,ext-irq-range = <32 200>;
};
iommu: mmsys_iommu@10205000 {
compatible = "mediatek,mt2701-m4u";
reg = <0 0x10205000 0 0x1000>;
......@@ -286,6 +297,48 @@ uart3: serial@11005000 {
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt2701-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11007000 0 0x70>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt2701-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11008000 0 0x70>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt2701-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11009000 0 0x70>,
<0 0x11000300 0 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt2701-spi";
#address-cells = <1>;
......@@ -334,6 +387,18 @@ bch: ecc@1100e000 {
status = "disabled";
};
nor_flash: spi@11014000 {
compatible = "mediatek,mt2701-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0xe0>;
clocks = <&pericfg CLK_PERI_FLASH>,
<&topckgen CLK_TOP_FLASH_SEL>;
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@11016000 {
compatible = "mediatek,mt2701-spi";
#address-cells = <1>;
......@@ -360,6 +425,104 @@ spi2: spi@11017000 {
status = "disabled";
};
afe: audio-controller@11220000 {
compatible = "mediatek,mt2701-audio";
reg = <0 0x11220000 0 0x2000>,
<0 0x112a0000 0 0x20000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
<&topckgen CLK_TOP_APLL_SEL>,
<&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>,
<&topckgen CLK_TOP_HADDS2PLL_98M>,
<&topckgen CLK_TOP_HADDS2PLL_294M>,
<&topckgen CLK_TOP_AUDPLL>,
<&topckgen CLK_TOP_AUDPLL_D4>,
<&topckgen CLK_TOP_AUDPLL_D8>,
<&topckgen CLK_TOP_AUDPLL_D16>,
<&topckgen CLK_TOP_AUDPLL_D24>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_SYSPLL1_D4>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
<&topckgen CLK_TOP_ASM_M_SEL>,
<&topckgen CLK_TOP_ASM_H_SEL>,
<&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_UNIVPLL2_D2>,
<&topckgen CLK_TOP_SYSPLL_D5>;
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_mux1_div",
"top_audio_mux2_div",
"top_audio_48k_timing",
"top_audio_44k_timing",
"top_audpll_mux_sel",
"top_apll_sel",
"top_aud1_pll_98M",
"top_aud2_pll_90M",
"top_hadds2_pll_98M",
"top_hadds2_pll_294M",
"top_audpll",
"top_audpll_d4",
"top_audpll_d8",
"top_audpll_d16",
"top_audpll_d24",
"top_audintbus_sel",
"clk_26m",
"top_syspll1_d4",
"top_aud_k1_src_sel",
"top_aud_k2_src_sel",
"top_aud_k3_src_sel",
"top_aud_k4_src_sel",
"top_aud_k5_src_sel",
"top_aud_k6_src_sel",
"top_aud_k1_src_div",
"top_aud_k2_src_div",
"top_aud_k3_src_div",
"top_aud_k4_src_div",
"top_aud_k5_src_div",
"top_aud_k6_src_div",
"top_aud_i2s1_mclk",
"top_aud_i2s2_mclk",
"top_aud_i2s3_mclk",
"top_aud_i2s4_mclk",
"top_aud_i2s5_mclk",
"top_aud_i2s6_mclk",
"top_asm_m_sel",
"top_asm_h_sel",
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt2701-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
......@@ -392,6 +555,20 @@ larb2: larb@15001000 {
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
};
jpegdec: jpegdec@15004000 {
compatible = "mediatek,mt2701-jpgdec";
reg = <0 0x15004000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
......
arch/arm/boot/dts/mt7623.dtsi
View file @ 226fe7c1
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