Commit 22dcc7d7 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'powerpc-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:

 - Fix PCIe MEM size for pci2 node on Turris 1.x boards

 - Two minor build fixes

Thanks to Christophe Leroy, Douglas Anderson, Pali Rohár, Petr Mladek,
and Randy Dunlap.

* tag 'powerpc-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc: dts: turris1x.dts: Fix PCIe MEM size for pci2 node
  powerpc: Include asm/nmi.c in mobility.c for watchdog_hardlockup_set_timeout_pct()
  powerpc: allow PPC_EARLY_DEBUG_CPM only when SERIAL_CPM=y
parents 70806ee1 abaa02fc
......@@ -240,7 +240,7 @@ config PPC_EARLY_DEBUG_40x
config PPC_EARLY_DEBUG_CPM
bool "Early serial debugging for Freescale CPM-based serial ports"
depends on SERIAL_CPM
depends on SERIAL_CPM=y
help
Select this to enable early debugging for Freescale chips
using a CPM-based serial port. This assumes that the bootwrapper
......
......@@ -476,12 +476,12 @@ pci2: pcie@ffe08000 {
* channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
* slot 1 (CN5), channels 2 and 3 to connector P600.
*
* P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller
* P2020 PCIe Root Port does not use PCIe MEM and xHCI controller
* uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
* So allocate 2MB of PCIe MEM for this PCIe bus.
* So allocate 128kB of PCIe MEM for this PCIe bus.
*/
reg = <0 0xffe08000 0 0x1000>;
ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */
ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00020000>, /* MEM */
<0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
pcie@0 {
......
......@@ -24,6 +24,7 @@
#include <linux/stringify.h>
#include <asm/machdep.h>
#include <asm/nmi.h>
#include <asm/rtas.h>
#include "pseries.h"
#include "vas.h" /* vas_migration_handler() */
......
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