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Commit 26410c67 authored by Maarten Lankhorst's avatar Maarten Lankhorst Committed by Ben Skeggs
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drm/nvd7/gr: initial support 

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent a32b2ffb
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Showing with 1930 additions and 20 deletions
drivers/gpu/drm/nouveau/Makefile
View file @ 26410c67
......@@ -203,6 +203,7 @@ nouveau-y += core/engine/graph/ctxnvc0.o
nouveau-y += core/engine/graph/ctxnvc1.o
nouveau-y += core/engine/graph/ctxnvc3.o
nouveau-y += core/engine/graph/ctxnvc8.o
nouveau-y += core/engine/graph/ctxnvd7.o
nouveau-y += core/engine/graph/ctxnvd9.o
nouveau-y += core/engine/graph/ctxnve4.o
nouveau-y += core/engine/graph/ctxnvf0.o
......@@ -220,6 +221,7 @@ nouveau-y += core/engine/graph/nvc0.o
nouveau-y += core/engine/graph/nvc1.o
nouveau-y += core/engine/graph/nvc3.o
nouveau-y += core/engine/graph/nvc8.o
nouveau-y += core/engine/graph/nvd7.o
nouveau-y += core/engine/graph/nvd9.o
nouveau-y += core/engine/graph/nve4.o
nouveau-y += core/engine/graph/nvf0.o
......
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
View file @ 26410c67
......@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
......
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c 0 → 100644
View file @ 26410c67
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
struct nvc0_graph_init
nvd7_grctx_init_unk40xx[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 1, 0x04, 0x00000000 },
{ 0x404098, 12, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf0000087 },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404130, 1, 0x04, 0x00000000 },
{ 0x404134, 1, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000055 },
{ 0x404168, 1, 0x04, 0x00000000 },
{ 0x404178, 2, 0x04, 0x00000000 },
{ 0x404200, 8, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_unk58xx[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180324 },
{ 0x405834, 1, 0x04, 0x08000000 },
{ 0x405838, 1, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_unk64xx[] = {
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 3, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x801a0078 },
{ 0x4064c4, 1, 0x04, 0x00c9ffff },
{ 0x4064d0, 8, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_gpc_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
{ 0x418410, 1, 0x04, 0x0fff0fff },
{ 0x418414, 1, 0x04, 0x02200fff },
{ 0x418450, 6, 0x04, 0x00000000 },
{ 0x418468, 1, 0x04, 0x00000001 },
{ 0x41846c, 2, 0x04, 0x00000000 },
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
{ 0x418704, 1, 0x04, 0x00000080 },
{ 0x418708, 3, 0x04, 0x00000000 },
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100018 },
{ 0x41891c, 1, 0x04, 0x00ff00ff },
{ 0x418924, 1, 0x04, 0x00000000 },
{ 0x418928, 1, 0x04, 0x00ffff00 },
{ 0x41892c, 1, 0x04, 0x0000ff00 },
{ 0x418b00, 1, 0x04, 0x00000006 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
{ 0x418b10, 1, 0x04, 0x020398a4 },
{ 0x418b14, 1, 0x04, 0x0e629062 },
{ 0x418b18, 1, 0x04, 0x0a418820 },
{ 0x418b1c, 1, 0x04, 0x000000e6 },
{ 0x418bb8, 1, 0x04, 0x00000103 },
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c6c, 1, 0x04, 0x00000001 },
{ 0x418c80, 1, 0x04, 0x20200004 },
{ 0x418c8c, 1, 0x04, 0x00000001 },
{ 0x419000, 1, 0x04, 0x00000780 },
{ 0x419004, 2, 0x04, 0x00000000 },
{ 0x419014, 1, 0x04, 0x00000004 },
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_tpc[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x00008000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0017f440 },
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000000f },
{ 0x419e50, 17, 0x04, 0x00000000 },
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00010110 },
{ 0x419f30, 11, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_unk[] = {
{ 0x41be24, 1, 0x04, 0x00000002 },
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00003fff },
{ 0x41bee4, 1, 0x04, 0x03240218 },
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
{ 0x41bf08, 1, 0x04, 0x020398a4 },
{ 0x41bf0c, 1, 0x04, 0x0e629062 },
{ 0x41bf10, 1, 0x04, 0x0a418820 },
{ 0x41bf14, 1, 0x04, 0x000000e6 },
{ 0x41bfd0, 1, 0x04, 0x00900103 },
{ 0x41bfe0, 1, 0x04, 0x00400001 },
{ 0x41bfe4, 1, 0x04, 0x00000000 },
{}
};
static void
nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
u32 magic[GPC_MAX][2];
u32 offset;
int gpc;
mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000018, 0, 0);
mmio_list(0x418808, 0x00000000, 8, 0);
mmio_list(0x41880c, 0x80000018, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
mmio_list(0x405830, 0x02180324, 0, 0);
mmio_list(0x4064c4, 0x00c9ffff, 0, 0);
for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
u16 magic1 = 0x0324 * priv->tpc_nr[gpc];
magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset;
magic[gpc][1] = 0x00000000 | (magic1 << 16);
offset += 0x0324 * priv->tpc_nr[gpc];
}
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
offset += 0x07ff * priv->tpc_nr[gpc];
}
mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */
}
void
nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
for (i = 0; oclass->hub[i]; i++)
nvc0_graph_mmio(priv, oclass->hub[i]);
for (i = 0; oclass->gpc[i]; i++)
nvc0_graph_mmio(priv, oclass->gpc[i]);
nv_wr32(priv, 0x404154, 0x00000000);
oclass->mods(priv, info);
nv_wr32(priv, 0x418c6c, 0x1);
nv_wr32(priv, 0x41980c, 0x10);
nv_wr32(priv, 0x41be08, 0x4);
nv_wr32(priv, 0x4064c0, 0x801a0078);
nv_wr32(priv, 0x405800, 0xf8000bf);
nv_wr32(priv, 0x419c00, 0xa);
nvc0_grctx_generate_tpcid(priv);
nvc0_grctx_generate_r406028(priv);
nv_wr32(priv, 0x40602c, 0x00000000);
nv_wr32(priv, 0x405874, 0x00000000);
nv_wr32(priv, 0x406030, 0x00000000);
nv_wr32(priv, 0x405878, 0x00000000);
nv_wr32(priv, 0x406034, 0x00000000);
nv_wr32(priv, 0x40587c, 0x00000000);
nvc0_grctx_generate_r4060a8(priv);
nve4_grctx_generate_r418bb8(priv);
nvc0_grctx_generate_r406800(priv);
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
nvc0_graph_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
nvc0_graph_mthd(priv, oclass->mthd);
nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
}
static struct nvc0_graph_init *
nvd7_grctx_init_hub[] = {
nvc0_grctx_init_base,
nvd7_grctx_init_unk40xx,
nvc0_grctx_init_unk44xx,
nvc0_grctx_init_unk46xx,
nvc0_grctx_init_unk47xx,
nvd7_grctx_init_unk58xx,
nvc0_grctx_init_unk60xx,
nvd7_grctx_init_unk64xx,
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvd9_grctx_init_rop,
};
struct nvc0_graph_init *
nvd7_grctx_init_gpc[] = {
nvd7_grctx_init_gpc_0,
nvc0_grctx_init_gpc_1,
nvd7_grctx_init_tpc,
nvd7_grctx_init_unk,
NULL
};
struct nouveau_oclass *
nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd7),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_context_ctor,
.dtor = nvc0_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvd7_grctx_generate_main,
.mods = nvd7_grctx_generate_mods,
.hub = nvd7_grctx_init_hub,
.gpc = nvd7_grctx_init_gpc,
.icmd = nvd9_grctx_init_icmd,
.mthd = nvd9_grctx_init_mthd,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
View file @ 26410c67
......@@ -41,7 +41,7 @@ gpc_id: .b32 0
tpc_count: .b32 0
tpc_mask: .b32 0
#ifdef NVGK
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
unk_count: .b32 1
unk_mask: .b32 1
#endif
......@@ -145,7 +145,7 @@ init:
add b32 $r2 $r14
add b32 $r3 $r14
#ifdef NVGK
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
// calculate per-UNK mmio context size
ld b32 $r14 D[$r0 + #unk_mmio_list_head]
ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
......@@ -342,7 +342,7 @@ ctx_xfer:
mov $r14 0x800 // stride = 0x800
call #mmctx_xfer
#ifdef NVGK
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
// per-UNK mmio context
xbit $r10 $flags $p1 // direction
or $r10 4 // last
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
View file @ 26410c67
......@@ -22,7 +22,9 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NVGF
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000000
#define CHIPSET GF100
#include "macros.fuc"
.section #nvc0_grgpc_data
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc 0 → 100644
View file @ 26410c67
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
#define CHIPSET GF117
#include "macros.fuc"
.section #nvd7_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #nvd7_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h 0 → 100644
View file @ 26410c67
uint32_t nvd7_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000001,
/* 0x0020: unk_mask */
0x00000001,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
uint32_t nvd7_grgpc_code[] = {
0x03060ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0x0489b808,
0xf00c1bf4,
0x21f502f7,
0x00f802ec,
/* 0x001c: queue_put_next */
0xb60798c4,
0x8dbb0384,
0x0880b600,
0x80008e80,
0x90b6018f,
0x0f94f001,
0xf801d980,
/* 0x0039: queue_get */
0x0131f400,
0x9800d898,
0x89b801d9,
0x210bf404,
0xb60789c4,
0x9dbb0394,
0x0890b600,
0x98009e98,
0x80b6019f,
0x0f84f001,
0xf400d880,
/* 0x0066: queue_get_done */
0x00f80132,
/* 0x0068: nv_rd32 */
0x0728b7f1,
0xb906b4b6,
0xc9f002ec,
0x00bcd01f,
/* 0x0078: nv_rd32_wait */
0xc800bccf,
0x1bf41fcc,
0x06a7f0fa,
0x010321f5,
0xf840bfcf,
/* 0x008d: nv_wr32 */
0x28b7f100,
0x06b4b607,
0xb980bfd0,
0xc9f002ec,
0x1ec9f01f,
/* 0x00a3: nv_wr32_wait */
0xcf00bcd0,
0xccc800bc,
0xfa1bf41f,
/* 0x00ae: watchdog_reset */
0x87f100f8,
0x84b60430,
0x1ff9f006,
0xf8008fd0,
/* 0x00bd: watchdog_clear */
0x3087f100,
0x0684b604,
0xf80080d0,
/* 0x00c9: wait_donez */
0x3c87f100,
0x0684b608,
0x99f094bd,
0x0089d000,
0x081887f1,
0xd00684b6,
/* 0x00e2: wait_donez_ne */
0x87f1008a,
0x84b60400,
0x0088cf06,
0xf4888aff,
0x87f1f31b,
0x84b6085c,
0xf094bd06,
0x89d00099,
/* 0x0103: wait_doneo */
0xf100f800,
0xb6083c87,
0x94bd0684,
0xd00099f0,
0x87f10089,
0x84b60818,
0x008ad006,
/* 0x011c: wait_doneo_e */
0x040087f1,
0xcf0684b6,
0x8aff0088,
0xf30bf488,
0x085c87f1,
0xbd0684b6,
0x0099f094,
0xf80089d0,
/* 0x013d: mmctx_size */
/* 0x013f: nv_mmctx_size_loop */
0x9894bd00,
0x85b600e8,
0x0180b61a,
0xbb0284b6,
0xe0b60098,
0x04efb804,
0xb9eb1bf4,
0x00f8029f,
/* 0x015c: mmctx_xfer */
0x083c87f1,
0xbd0684b6,
0x0199f094,
0xf10089d0,
0xb6071087,
0x94bd0684,
0xf405bbfd,
0x8bd0090b,
0x0099f000,
/* 0x0180: mmctx_base_disabled */
0xf405eefd,
0x8ed00c0b,
0xc08fd080,
/* 0x018f: mmctx_multi_disabled */
0xb70199f0,
0xc8010080,
0xb4b600ab,
0x0cb9f010,
0xb601aec8,
0xbefd11e4,
0x008bd005,
/* 0x01a8: mmctx_exec_loop */
/* 0x01a8: mmctx_wait_free */
0xf0008ecf,
0x0bf41fe4,
0x00ce98fa,
0xd005e9fd,
0xc0b6c08e,
0x04cdb804,
0xc8e81bf4,
0x1bf402ab,
/* 0x01c9: mmctx_fini_wait */
0x008bcf18,
0xb01fb4f0,
0x1bf410b4,
0x02a7f0f7,
0xf4c921f4,
/* 0x01de: mmctx_stop */
0xabc81b0e,
0x10b4b600,
0xf00cb9f0,
0x8bd012b9,
/* 0x01ed: mmctx_stop_wait */
0x008bcf00,
0xf412bbc8,
/* 0x01f6: mmctx_done */
0x87f1fa1b,
0x84b6085c,
0xf094bd06,
0x89d00199,
/* 0x0207: strand_wait */
0xf900f800,
0x02a7f0a0,
0xfcc921f4,
/* 0x0213: strand_pre */
0xf100f8a0,
0xf04afc87,
0x97f00283,
0x0089d00c,
0x020721f5,
/* 0x0226: strand_post */
0x87f100f8,
0x83f04afc,
0x0d97f002,
0xf50089d0,
0xf8020721,
/* 0x0239: strand_set */
0xfca7f100,
0x02a3f04f,
0x0500aba2,
0xd00fc7f0,
0xc7f000ac,
0x00bcd00b,
0x020721f5,
0xf000aed0,
0xbcd00ac7,
0x0721f500,
/* 0x0263: strand_ctx_init */
0xf100f802,
0xb6083c87,
0x94bd0684,
0xd00399f0,
0x21f50089,
0xe7f00213,
0x3921f503,
0xfca7f102,
0x02a3f046,
0x0400aba0,
0xf040a0d0,
0xbcd001c7,
0x0721f500,
0x010c9202,
0xf000acd0,
0xbcd002c7,
0x0721f500,
0x2621f502,
0x8087f102,
0x0684b608,
0xb70089cf,
0x95220080,
/* 0x02ba: ctx_init_strand_loop */
0x8ed008fe,
0x408ed000,
0xb6808acf,
0xa0b606a5,
0x00eabb01,
0xb60480b6,
0x1bf40192,
0x08e4b6e8,
0xf1f2efbc,
0xb6085c87,
0x94bd0684,
0xd00399f0,
0x00f80089,
/* 0x02ec: error */
0xe7f1e0f9,
0xe3f09814,
0x8d21f440,
0x041ce0b7,
0xf401f7f0,
0xe0fc8d21,
/* 0x0306: init */
0x04bd00f8,
0xf10004fe,
0xf0120017,
0x12d00227,
0x2317f100,
0x0010fe04,
0x040017f1,
0xf0c010d0,
0x12d00427,
0x1031f400,
0x060817f1,
0xcf0614b6,
0x37f00012,
0x1f24f001,
0xb60432bb,
0x02800132,
0x06038005,
0x040010b7,
0x800012cf,
0x27f10402,
0x24b60800,
0x4022cf06,
0x47f134bd,
0x44b60700,
0x08259506,
0xd00045d0,
0x0e984045,
0x010f9800,
0x013d21f5,
0xbb002fbb,
0x0e98003f,
0x020f9801,
0x013d21f5,
0xfd050e98,
0x2ebb00ef,
0x003ebb00,
0x98020e98,
0x21f5030f,
0x0e98013d,
0x00effd07,
0xbb002ebb,
0x40b7003e,
0x35b61300,
0x0043d002,
0xb60825b6,
0x20b60635,
0x0130b601,
0xb60824b6,
0x2fb90834,
0x6321f502,
0x003fbb02,
0x080017f1,
0xd00614b6,
0x10b74013,
0x24bd0800,
0xd01f29f0,
/* 0x03e6: main */
0x31f40012,
0x0028f400,
0xf424d7f0,
0x01f43921,
0x04e4b0f4,
0xfe1e18f4,
0x27f00181,
0xfd20bd06,
0xe4b60412,
0x051efd01,
0xf50018fe,
0xf404a821,
/* 0x0416: main_not_ctx_xfer */
0xef94d30e,
0x01f5f010,
0x02ec21f5,
/* 0x0423: ih */
0xf9c60ef4,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x0acff0f9,
0x04abc480,
0xf11d0bf4,
0xf01900b7,
0xbecf24d7,
0x00bfcf40,
0xb70421f4,
0xf00400b0,
0xbed001e7,
/* 0x0459: ih_no_fifo */
0x400ad000,
0xe0fcf0fc,
0xb0fcd0fc,
0x90fca0fc,
0x88fe80fc,
0xf480fc00,
0x01f80032,
/* 0x0474: hub_barrier_done */
0x9801f7f0,
0xfebb040e,
0x18e7f104,
0x40e3f094,
0xf88d21f4,
/* 0x0489: ctx_redswitch */
0x14e7f100,
0x06e4b606,
0xd020f7f0,
0xf7f000ef,
/* 0x0499: ctx_redswitch_delay */
0x01f2b608,
0xf1fd1bf4,
0xd00a20f7,
0x00f800ef,
/* 0x04a8: ctx_xfer */
0x0a0417f1,
0xd00614b6,
0x11f4001f,
0x8921f507,
/* 0x04b9: ctx_xfer_not_load */
0xfc17f104,
0x0213f04a,
0xd00c27f0,
0x21f50012,
0x27f10207,
0x23f047fc,
0x0020d002,
0xb6012cf0,
0x12d00320,
0x01acf000,
0xf002a5f0,
0xb3f000b7,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x010d9800,
0xf500e7f0,
0xf0015c21,
0xb7f101ac,
0xb3f04000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x020d9801,
0xf1060f98,
0xf50800e7,
0xf0015c21,
0xa5f001ac,
0x00b7f104,
0x50b3f030,
0xb6040c98,
0xbcbb0fc4,
0x020c9800,
0x98030d98,
0xe7f1080f,
0x21f50200,
0x21f5015c,
0x01f40207,
0x1412f406,
/* 0x0554: ctx_xfer_post */
0x4afc17f1,
0xf00213f0,
0x12d00d27,
0x0721f500,
/* 0x0565: ctx_xfer_done */
0x7421f502,
0x0000f804,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
View file @ 26410c67
......@@ -22,7 +22,9 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NVGK
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
#define CHIPSET GK100
#include "macros.fuc"
.section #nve0_grgpc_data
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
View file @ 26410c67
......@@ -377,7 +377,7 @@ ih:
bclr $flags $p0
iret
#ifdef NVGF
#if CHIPSET < GK100
// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
ctx_4160s:
mov $r14 0x4160
......@@ -541,7 +541,7 @@ ctx_load:
// In: $r2 channel address
//
ctx_chan:
#ifdef NVGF
#if CHIPSET < GK100
call #ctx_4160s
#endif
call #ctx_load
......@@ -555,7 +555,7 @@ ctx_chan:
iord $r2 I[$r1 + 0x000]
or $r2 $r2
bra ne #ctx_chan_wait
#ifdef NVGF
#if CHIPSET < GK100
call #ctx_4160c
#endif
ret
......@@ -634,7 +634,7 @@ ctx_xfer:
ctx_xfer_pre:
mov $r15 0x10
call #ctx_86c
#ifdef NVGF
#if CHIPSET < GK100
call #ctx_4160s
#endif
bra not $p1 #ctx_xfer_exec
......@@ -725,7 +725,7 @@ ctx_xfer:
call #ctx_mmio_exec
ctx_xfer_no_post_mmio:
#ifdef NVGF
#if CHIPSET < GK100
call #ctx_4160c
#endif
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
View file @ 26410c67
......@@ -22,7 +22,7 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NVGF
#define CHIPSET GF100
#include "macros.fuc"
.section #nvc0_grhub_data
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc 0 → 100644
View file @ 26410c67
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GF117
#include "macros.fuc"
.section #nvd7_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #nvd7_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h 0 → 100644
View file @ 26410c67
This diff is collapsed.
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
View file @ 26410c67
......@@ -22,7 +22,7 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NVGK
#define CHIPSET GK100
#include "macros.fuc"
.section #nve0_grhub_data
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
View file @ 26410c67
......@@ -24,6 +24,10 @@
#include "os.h"
#define GF100 0xc0
#define GF117 0xd7
#define GK100 0xe0
#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2)
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file @ 26410c67
......@@ -282,6 +282,12 @@ nvc0_graph_init_unk88xx[] = {
{}
};
struct nvc0_graph_init
nvc0_graph_tpc_0[] = {
{ 0x50405c, 1, 0x04, 0x00000001 },
{}
};
void
nvc0_graph_mmio(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init)
{
......@@ -982,9 +988,6 @@ nvc0_graph_init(struct nouveau_object *object)
for (i = 0; oclass->mmio[i]; i++)
nvc0_graph_mmio(priv, oclass->mmio[i]);
/* affects TFB offset queries */
nv_wr32(priv, TPC_UNIT(0, 0, 0x5c), 1);
memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
do {
......@@ -1008,7 +1011,11 @@ nvc0_graph_init(struct nouveau_object *object)
nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
if (nv_device(priv)->chipset != 0xd7)
nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
else
nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
nv_wr32(priv, 0x400500, 0x00010001);
......@@ -1123,10 +1130,9 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nvc0_graph_oclass *oclass = (void *)bclass;
struct nouveau_device *device = nv_device(parent);
struct nvc0_graph_priv *priv;
bool enable = device->chipset != 0xd7;
int ret, i;
ret = nouveau_graph_create(parent, engine, bclass, enable, &priv);
ret = nouveau_graph_create(parent, engine, bclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
......@@ -1199,6 +1205,7 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
case 0xcf: /* 4/0/0/0, 3 */
priv->magic_not_rop_nr = 0x03;
break;
case 0xd7:
case 0xd9: /* 1/0/0/0, 1 */
priv->magic_not_rop_nr = 0x01;
break;
......@@ -1221,6 +1228,7 @@ nvc0_graph_init_mmio[] = {
nvc0_graph_init_gpc,
nvc0_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
};
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
View file @ 26410c67
......@@ -193,9 +193,11 @@ extern struct nvc0_graph_init nvc0_graph_init_unk58xx[];
extern struct nvc0_graph_init nvc0_graph_init_unk80xx[];
extern struct nvc0_graph_init nvc0_graph_init_gpc[];
extern struct nvc0_graph_init nvc0_graph_init_unk88xx[];
extern struct nvc0_graph_init nvc0_graph_tpc_0[];
extern struct nvc0_graph_init nvc3_graph_init_unk58xx[];
extern struct nvc0_graph_init nvd9_graph_init_unk58xx[];
extern struct nvc0_graph_init nvd9_graph_init_unk64xx[];
extern struct nvc0_graph_init nve4_graph_init_regs[];
......@@ -209,6 +211,7 @@ void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvc0_grctx_oclass;
......@@ -244,8 +247,11 @@ extern struct nouveau_oclass *nvc8_grctx_oclass;
extern struct nvc0_graph_init nvc8_grctx_init_9197[];
extern struct nvc0_graph_init nvc8_grctx_init_9297[];
extern struct nouveau_oclass *nvd7_grctx_oclass;
extern struct nouveau_oclass *nvd9_grctx_oclass;
extern struct nvc0_graph_init nvd9_grctx_init_rop[];
extern struct nvc0_graph_mthd nvd9_grctx_init_mthd[];
void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
View file @ 26410c67
......@@ -123,6 +123,7 @@ nvc1_graph_init_mmio[] = {
nvc1_graph_init_gpc,
nvc1_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
};
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c
View file @ 26410c67
......@@ -89,6 +89,7 @@ nvc3_graph_init_mmio[] = {
nvc0_graph_init_gpc,
nvc3_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
};
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
View file @ 26410c67
......@@ -120,6 +120,7 @@ nvc8_graph_init_mmio[] = {
nvc8_graph_init_gpc,
nvc8_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
};
......
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c 0 → 100644
View file @ 26410c67
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
#include "fuc/hubnvd7.fuc.h"
struct nvc0_graph_ucode
nvd7_graph_fecs_ucode = {
.code.data = nvd7_grhub_code,
.code.size = sizeof(nvd7_grhub_code),
.data.data = nvd7_grhub_data,
.data.size = sizeof(nvd7_grhub_data),
};
#include "fuc/gpcnvd7.fuc.h"
struct nvc0_graph_ucode
nvd7_graph_gpccs_ucode = {
.code.data = nvd7_grgpc_code,
.code.size = sizeof(nvd7_grgpc_code),
.data.data = nvd7_grgpc_data,
.data.size = sizeof(nvd7_grgpc_data),
};
static struct nvc0_graph_init
nvd7_graph_init_gpc[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 },
{ 0x4184a4, 2, 0x04, 0x00000000 },
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
{ 0x418384, 1, 0x04, 0x00000000 },
{ 0x418814, 3, 0x04, 0x00000000 },
{ 0x418b04, 1, 0x04, 0x00000000 },
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000001 },
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
{ 0x418980, 1, 0x04, 0x77777770 },
{ 0x418984, 3, 0x04, 0x77777777 },
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 1, 0x04, 0x00000000 },
{ 0x418c68, 1, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{ 0x418cb4, 2, 0x04, 0x00000000 },
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 1, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418f20, 2, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000003 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{ 0x418e1c, 1, 0x04, 0x00000000 },
{ 0x418e20, 1, 0x04, 0x00000000 },
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd7_graph_init_tpc[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc8 },
{ 0x419850, 2, 0x04, 0x00000000 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x02001100 },
{ 0x419eac, 1, 0x04, 0x11100702 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0e063818 },
{ 0x419ecc, 1, 0x04, 0x0e060e06 },
{ 0x419ed0, 1, 0x04, 0x00003818 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd7_graph_init_tpc_0[] = {
{ 0x40402c, 1, 0x04, 0x00000000 },
{ 0x4040f0, 1, 0x04, 0x00000000 },
{ 0x404174, 1, 0x04, 0x00000000 },
{ 0x503018, 1, 0x04, 0x00000001 },
{}
};
static struct nvc0_graph_init *
nvd7_graph_init_mmio[] = {
nvc0_graph_init_regs,
nvc0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvd9_graph_init_unk64xx,
nvd9_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvd7_graph_init_gpc,
nvd7_graph_init_tpc,
nve4_graph_init_unk,
nvc0_graph_init_unk88xx,
nvd7_graph_init_tpc_0,
NULL
};
struct nouveau_oclass *
nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
.base.handle = NV_ENGINE(GR, 0xd7),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_ctor,
.dtor = nvc0_graph_dtor,
.init = nvc0_graph_init,
.fini = _nouveau_graph_fini,
},
.cclass = &nvd7_grctx_oclass,
.sclass = nvc8_graph_sclass,
.mmio = nvd7_graph_init_mmio,
.fecs.ucode = &nvd7_graph_fecs_ucode,
.gpccs.ucode = &nvd7_graph_gpccs_ucode,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
View file @ 26410c67
......@@ -34,7 +34,7 @@ nvd9_graph_init_unk64xx[] = {
{}
};
static struct nvc0_graph_init
struct nvc0_graph_init
nvd9_graph_init_unk58xx[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
......@@ -144,6 +144,7 @@ nvd9_graph_init_mmio[] = {
nvd9_graph_init_gpc,
nvd9_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
};
......
drivers/gpu/drm/nouveau/core/include/engine/graph.h
View file @ 26410c67
......@@ -65,6 +65,7 @@ extern struct nouveau_oclass *nvc0_graph_oclass;
extern struct nouveau_oclass *nvc1_graph_oclass;
extern struct nouveau_oclass *nvc3_graph_oclass;
extern struct nouveau_oclass *nvc8_graph_oclass;
extern struct nouveau_oclass *nvd7_graph_oclass;
extern struct nouveau_oclass *nvd9_graph_oclass;
extern struct nouveau_oclass *nve4_graph_oclass;
extern struct nouveau_oclass *nvf0_graph_oclass;
......
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