Commit 270fc77e authored by Yu Chien Peter Lin's avatar Yu Chien Peter Lin Committed by Palmer Dabbelt

riscv: dts: renesas: Add Andes PMU extension for r9a07g043f

xandespmu stands for Andes Performance Monitor Unit extension.
Based on the added Andes PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.
Signed-off-by: default avatarYu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240222083946.3977135-10-peterlin@andestech.comSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 61609bf2
...@@ -27,7 +27,7 @@ cpu0: cpu@0 { ...@@ -27,7 +27,7 @@ cpu0: cpu@0 {
riscv,isa-base = "rv64i"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei", "zicntr", "zicsr", "zifencei",
"zihpm"; "zihpm", "xandespmu";
mmu-type = "riscv,sv39"; mmu-type = "riscv,sv39";
i-cache-size = <0x8000>; i-cache-size = <0x8000>;
i-cache-line-size = <0x40>; i-cache-line-size = <0x40>;
......
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