Commit 286ce0ac authored by Russell King's avatar Russell King Committed by Russell King
parents d5b56233 26a55226
...@@ -121,20 +121,22 @@ int __init pxa_init_dma(int num_ch) ...@@ -121,20 +121,22 @@ int __init pxa_init_dma(int num_ch)
if (dma_channels == NULL) if (dma_channels == NULL)
return -ENOMEM; return -ENOMEM;
ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
if (ret) {
printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
kfree(dma_channels);
return ret;
}
/* dma channel priorities on pxa2xx processors: /* dma channel priorities on pxa2xx processors:
* ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH * ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
* ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM * ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
* ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW * ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
*/ */
for (i = 0; i < num_ch; i++) for (i = 0; i < num_ch; i++) {
DCSR(i) = 0;
dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
}
ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
if (ret) {
printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
kfree(dma_channels);
return ret;
}
num_dma_channels = num_ch; num_dma_channels = num_ch;
return 0; return 0;
......
#ifndef __ASM_ARCH_REGS_AC97_H #ifndef __ASM_ARCH_REGS_AC97_H
#define __ASM_ARCH_REGS_AC97_H #define __ASM_ARCH_REGS_AC97_H
#include <mach/hardware.h>
/* /*
* AC97 Controller registers * AC97 Controller registers
*/ */
......
...@@ -41,6 +41,9 @@ ...@@ -41,6 +41,9 @@
#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
#endif
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_EDSS (1 << 20) /* Extended data size select */ #define SSCR0_EDSS (1 << 20) /* Extended data size select */
#define SSCR0_NCS (1 << 21) /* Network clock select */ #define SSCR0_NCS (1 << 21) /* Network clock select */
#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
......
...@@ -88,13 +88,13 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { ...@@ -88,13 +88,13 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0); static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
static struct clk_lookup common_clkregs[] = { static struct clk_lookup common_clkregs[] = {
INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", "NANDCLK"), INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
}; };
static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
static struct clk_lookup pxa310_clkregs[] = { static struct clk_lookup pxa310_clkregs[] = {
INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", "MMCCLK"), INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", NULL),
}; };
static int __init pxa300_init(void) static int __init pxa300_init(void)
......
...@@ -83,7 +83,7 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { ...@@ -83,7 +83,7 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0); static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
static struct clk_lookup pxa320_clkregs[] = { static struct clk_lookup pxa320_clkregs[] = {
INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", "NANDCLK"), INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
}; };
static int __init pxa320_init(void) static int __init pxa320_init(void)
......
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