Commit 288be97c authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Will Deacon

arm64/lib: copy_page: use consistent prefetch stride

The optional prefetch instructions in the copy_page() routine are
inconsistent: at the start of the function, two cachelines are
prefetched beyond the one being loaded in the first iteration, but
in the loop, the prefetch is one more line ahead. This appears to
be unintentional, so let's fix it.

While at it, fix the comment style and white space.
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent ece4b206
...@@ -30,9 +30,10 @@ ...@@ -30,9 +30,10 @@
*/ */
ENTRY(copy_page) ENTRY(copy_page)
alternative_if ARM64_HAS_NO_HW_PREFETCH alternative_if ARM64_HAS_NO_HW_PREFETCH
# Prefetch two cache lines ahead. // Prefetch three cache lines ahead.
prfm pldl1strm, [x1, #128] prfm pldl1strm, [x1, #128]
prfm pldl1strm, [x1, #256] prfm pldl1strm, [x1, #256]
prfm pldl1strm, [x1, #384]
alternative_else_nop_endif alternative_else_nop_endif
ldp x2, x3, [x1] ldp x2, x3, [x1]
...@@ -50,7 +51,7 @@ alternative_else_nop_endif ...@@ -50,7 +51,7 @@ alternative_else_nop_endif
subs x18, x18, #128 subs x18, x18, #128
alternative_if ARM64_HAS_NO_HW_PREFETCH alternative_if ARM64_HAS_NO_HW_PREFETCH
prfm pldl1strm, [x1, #384] prfm pldl1strm, [x1, #384]
alternative_else_nop_endif alternative_else_nop_endif
stnp x2, x3, [x0] stnp x2, x3, [x0]
......
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