Commit 28bb7c55 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Linus Walleij

pinctrl: qcom: lpass-lpi: split slew rate set to separate function

Setting slew rate for each pin will grow with upcoming Qualcomm SoCs,
so split the code responsible for this into separate function for easier
readability and maintenance.
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231013145935.220945-2-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 22a4a9ed
...@@ -186,6 +186,35 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, ...@@ -186,6 +186,35 @@ static int lpi_config_get(struct pinctrl_dev *pctldev,
return 0; return 0;
} }
static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
const struct lpi_pingroup *g,
unsigned int group, unsigned int slew)
{
unsigned long sval;
int slew_offset;
if (slew > LPI_SLEW_RATE_MAX) {
dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",
slew, group);
return -EINVAL;
}
slew_offset = g->slew_offset;
if (slew_offset == LPI_NO_SLEW)
return 0;
mutex_lock(&pctrl->lock);
sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
sval |= slew << slew_offset;
iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
mutex_unlock(&pctrl->lock);
return 0;
}
static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
unsigned long *configs, unsigned int nconfs) unsigned long *configs, unsigned int nconfs)
{ {
...@@ -193,8 +222,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, ...@@ -193,8 +222,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
bool value, output_enabled = false; bool value, output_enabled = false;
const struct lpi_pingroup *g; const struct lpi_pingroup *g;
unsigned long sval; int i, ret;
int i, slew_offset;
u32 val; u32 val;
g = &pctrl->data->groups[group]; g = &pctrl->data->groups[group];
...@@ -226,24 +254,9 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, ...@@ -226,24 +254,9 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
strength = arg; strength = arg;
break; break;
case PIN_CONFIG_SLEW_RATE: case PIN_CONFIG_SLEW_RATE:
if (arg > LPI_SLEW_RATE_MAX) { ret = lpi_config_set_slew_rate(pctrl, g, group, arg);
dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n", if (ret)
arg, group); return ret;
return -EINVAL;
}
slew_offset = g->slew_offset;
if (slew_offset == LPI_NO_SLEW)
break;
mutex_lock(&pctrl->lock);
sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
sval |= arg << slew_offset;
iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
mutex_unlock(&pctrl->lock);
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
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