Commit 2a29f9d6 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman

ARM: dts: r8a7794: add MSTP5 clocks

Add some MSTP5 clocks to the R8A7794 device tree.
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 0b1f0e37
...@@ -1204,6 +1204,15 @@ mstp4_clks: mstp4_clks@e6150140 { ...@@ -1204,6 +1204,15 @@ mstp4_clks: mstp4_clks@e6150140 {
clock-indices = <R8A7794_CLK_IRQC>; clock-indices = <R8A7794_CLK_IRQC>;
clock-output-names = "irqc"; clock-output-names = "irqc";
}; };
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
clocks = <&hp_clk>, <&extal_clk>, <&p_clk>;
#clock-cells = <1>;
clock-indices = <R8A7794_CLK_AUDIO_DMAC0
R8A7794_CLK_PWM>;
clock-output-names = "audmac0", "pwm";
};
mstp7_clks: mstp7_clks@e615014c { mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
......
...@@ -67,6 +67,7 @@ ...@@ -67,6 +67,7 @@
#define R8A7794_CLK_IRQC 7 #define R8A7794_CLK_IRQC 7
/* MSTP5 */ /* MSTP5 */
#define R8A7794_CLK_AUDIO_DMAC0 2
#define R8A7794_CLK_PWM 23 #define R8A7794_CLK_PWM 23
/* MSTP7 */ /* MSTP7 */
......
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