Commit 2a346706 authored by Dave Airlie's avatar Dave Airlie

Merge tag 'mediatek-drm-2016-06-20' of git://git.pengutronix.de/git/pza/linux into drm-next

MT8173 HDMI support

- device tree binding documentation for MT8173 HDMI encoder, CEC, DDC,
  and PHY
- drivers for MT8173 HDMI encoder, CEC (HPD only for now), DDC, and PHY
- enable HDMI output via a custom SMCCC call
- add ddc-i2c-bus property to HDMI connector device tree binding

* tag 'mediatek-drm-2016-06-20' of git://git.pengutronix.de/git/pza/linux:
  dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
  drm/mediatek: enable hdmi output control bit
  drm/mediatek: Add HDMI support
  dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
parents 6559436d 9a449e0d
...@@ -8,6 +8,7 @@ Required properties: ...@@ -8,6 +8,7 @@ Required properties:
Optional properties: Optional properties:
- label: a symbolic name for the connector - label: a symbolic name for the connector
- hpd-gpios: HPD GPIO number - hpd-gpios: HPD GPIO number
- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
Required nodes: Required nodes:
- Video port for HDMI input - Video port for HDMI input
......
Mediatek HDMI Encoder
=====================
The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
its parallel input.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi".
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
- phys: phandle link to the HDMI PHY node.
See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
- phy-names: must contain "hdmi"
- mediatek,syscon-hdmi: phandle link and register offset to the system
configuration registers. For mt8173 this must be offset 0x900 into the
MMSYS_CONFIG region: <&mmsys 0x900>.
- ports: A node containing input and output port nodes with endpoint
definitions as documented in Documentation/devicetree/bindings/graph.txt.
- port@0: The input port in the ports node should be connected to a DPI output
port.
- port@1: The output port in the ports node should be connected to the input
port of a connector node that contains a ddc-i2c-bus property, or to the
input port of an attached bridge chip, such as a SlimPort transmitter.
HDMI CEC
========
The HDMI CEC controller handles hotplug detection and CEC communication.
Required properties:
- compatible: Should be "mediatek,<chip>-cec"
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clock
HDMI DDC
========
The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
- reg: Physical base address and length of the controller's registers
- clocks: device clock
- clock-names: Should be "ddc-i2c".
HDMI PHY
========
The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
output and drives the HDMI pads.
Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"
- clock-output-names: must be "hdmitx_dig_cts" on mt8173
- #phy-cells: must be <0>
- #clock-cells: must be <0>
Optional properties:
- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
Example:
cec: cec@10013000 {
compatible = "mediatek,mt8173-cec";
reg = <0 0x10013000 0 0xbc>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_CEC>;
};
hdmi_phy: hdmi-phy@10209100 {
compatible = "mediatek,mt8173-hdmi-phy";
reg = <0 0x10209100 0 0x24>;
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
clock-names = "pll_ref";
clock-output-names = "hdmitx_dig_cts";
mediatek,ibias = <0xa>;
mediatek,ibias_up = <0x1c>;
#clock-cells = <0>;
#phy-cells = <0>;
};
hdmi_ddc0: i2c@11012000 {
compatible = "mediatek,mt8173-hdmi-ddc";
reg = <0 0x11012000 0 0x1c>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_I2C5>;
clock-names = "ddc-i2c";
};
hdmi0: hdmi@14025000 {
compatible = "mediatek,mt8173-hdmi";
reg = <0 0x14025000 0 0x400>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
<&mmsys CLK_MM_HDMI_PLLCK>,
<&mmsys CLK_MM_HDMI_AUDIO>,
<&mmsys CLK_MM_HDMI_SPDIF>;
clock-names = "pixel", "pll", "bclk", "spdif";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pin>;
phys = <&hdmi_phy>;
phy-names = "hdmi";
mediatek,syscon-hdmi = <&mmsys 0x900>;
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
assigned-clock-parents = <&hdmi_phy>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi0_in: endpoint {
remote-endpoint = <&dpi0_out>;
};
};
port@1 {
reg = <1>;
hdmi0_out: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
};
};
connector {
compatible = "hdmi-connector";
type = "a";
ddc-i2c-bus = <&hdmiddc0>;
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi0_out>;
};
};
};
...@@ -13,3 +13,11 @@ config DRM_MEDIATEK ...@@ -13,3 +13,11 @@ config DRM_MEDIATEK
The module will be called mediatek-drm The module will be called mediatek-drm
This driver provides kernel mode setting and This driver provides kernel mode setting and
buffer management to userspace. buffer management to userspace.
config DRM_MEDIATEK_HDMI
tristate "DRM HDMI Support for Mediatek SoCs"
depends on DRM_MEDIATEK
select SND_SOC_HDMI_CODEC if SND_SOC
select GENERIC_PHY
help
DRM/KMS HDMI driver for Mediatek SoCs
...@@ -12,3 +12,10 @@ mediatek-drm-y := mtk_disp_ovl.o \ ...@@ -12,3 +12,10 @@ mediatek-drm-y := mtk_disp_ovl.o \
mtk_dpi.o mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
mediatek-drm-hdmi-objs := mtk_cec.o \
mtk_hdmi.o \
mtk_hdmi_ddc.o \
mtk_mt8173_hdmi_phy.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include "mtk_cec.h"
#define TR_CONFIG 0x00
#define CLEAR_CEC_IRQ BIT(15)
#define CEC_CKGEN 0x04
#define CEC_32K_PDN BIT(19)
#define PDN BIT(16)
#define RX_EVENT 0x54
#define HDMI_PORD BIT(25)
#define HDMI_HTPLG BIT(24)
#define HDMI_PORD_INT_EN BIT(9)
#define HDMI_HTPLG_INT_EN BIT(8)
#define RX_GEN_WD 0x58
#define HDMI_PORD_INT_32K_STATUS BIT(26)
#define RX_RISC_INT_32K_STATUS BIT(25)
#define HDMI_HTPLG_INT_32K_STATUS BIT(24)
#define HDMI_PORD_INT_32K_CLR BIT(18)
#define RX_INT_32K_CLR BIT(17)
#define HDMI_HTPLG_INT_32K_CLR BIT(16)
#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
#define RX_RISC_INT_32K_STA_MASK BIT(9)
#define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
#define HDMI_PORD_INT_32K_EN BIT(2)
#define RX_INT_32K_EN BIT(1)
#define HDMI_HTPLG_INT_32K_EN BIT(0)
#define NORMAL_INT_CTRL 0x5C
#define HDMI_HTPLG_INT_STA BIT(0)
#define HDMI_PORD_INT_STA BIT(1)
#define HDMI_HTPLG_INT_CLR BIT(16)
#define HDMI_PORD_INT_CLR BIT(17)
#define HDMI_FULL_INT_CLR BIT(20)
struct mtk_cec {
void __iomem *regs;
struct clk *clk;
int irq;
bool hpd;
void (*hpd_event)(bool hpd, struct device *dev);
struct device *hdmi_dev;
spinlock_t lock;
};
static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
unsigned int bits)
{
void __iomem *reg = cec->regs + offset;
u32 tmp;
tmp = readl(reg);
tmp &= ~bits;
writel(tmp, reg);
}
static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
unsigned int bits)
{
void __iomem *reg = cec->regs + offset;
u32 tmp;
tmp = readl(reg);
tmp |= bits;
writel(tmp, reg);
}
static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
unsigned int val, unsigned int mask)
{
u32 tmp = readl(cec->regs + offset) & ~mask;
tmp |= val & mask;
writel(val, cec->regs + offset);
}
void mtk_cec_set_hpd_event(struct device *dev,
void (*hpd_event)(bool hpd, struct device *dev),
struct device *hdmi_dev)
{
struct mtk_cec *cec = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&cec->lock, flags);
cec->hdmi_dev = hdmi_dev;
cec->hpd_event = hpd_event;
spin_unlock_irqrestore(&cec->lock, flags);
}
bool mtk_cec_hpd_high(struct device *dev)
{
struct mtk_cec *cec = dev_get_drvdata(dev);
unsigned int status;
status = readl(cec->regs + RX_EVENT);
return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
}
static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
{
mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
}
static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
{
mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
}
static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
{
mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
}
static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
{
mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
usleep_range(5, 10);
mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
}
static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
{
void (*hpd_event)(bool hpd, struct device *dev);
struct device *hdmi_dev;
unsigned long flags;
spin_lock_irqsave(&cec->lock, flags);
hpd_event = cec->hpd_event;
hdmi_dev = cec->hdmi_dev;
spin_unlock_irqrestore(&cec->lock, flags);
if (hpd_event)
hpd_event(hpd, hdmi_dev);
}
static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
{
struct device *dev = arg;
struct mtk_cec *cec = dev_get_drvdata(dev);
bool hpd;
mtk_cec_clear_htplg_irq(cec);
hpd = mtk_cec_hpd_high(dev);
if (cec->hpd != hpd) {
dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
cec->hpd, hpd);
cec->hpd = hpd;
mtk_cec_hpd_event(cec, hpd);
}
return IRQ_HANDLED;
}
static int mtk_cec_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_cec *cec;
struct resource *res;
int ret;
cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
if (!cec)
return -ENOMEM;
platform_set_drvdata(pdev, cec);
spin_lock_init(&cec->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
cec->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(cec->regs)) {
ret = PTR_ERR(cec->regs);
dev_err(dev, "Failed to ioremap cec: %d\n", ret);
return ret;
}
cec->clk = devm_clk_get(dev, NULL);
if (IS_ERR(cec->clk)) {
ret = PTR_ERR(cec->clk);
dev_err(dev, "Failed to get cec clock: %d\n", ret);
return ret;
}
cec->irq = platform_get_irq(pdev, 0);
if (cec->irq < 0) {
dev_err(dev, "Failed to get cec irq: %d\n", cec->irq);
return cec->irq;
}
ret = devm_request_threaded_irq(dev, cec->irq, NULL,
mtk_cec_htplg_isr_thread,
IRQF_SHARED | IRQF_TRIGGER_LOW |
IRQF_ONESHOT, "hdmi hpd", dev);
if (ret) {
dev_err(dev, "Failed to register cec irq: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(cec->clk);
if (ret) {
dev_err(dev, "Failed to enable cec clock: %d\n", ret);
return ret;
}
mtk_cec_htplg_irq_init(cec);
mtk_cec_htplg_irq_enable(cec);
return 0;
}
static int mtk_cec_remove(struct platform_device *pdev)
{
struct mtk_cec *cec = platform_get_drvdata(pdev);
mtk_cec_htplg_irq_disable(cec);
clk_disable_unprepare(cec->clk);
return 0;
}
static const struct of_device_id mtk_cec_of_ids[] = {
{ .compatible = "mediatek,mt8173-cec", },
{}
};
struct platform_driver mtk_cec_driver = {
.probe = mtk_cec_probe,
.remove = mtk_cec_remove,
.driver = {
.name = "mediatek-cec",
.of_match_table = mtk_cec_of_ids,
},
};
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MTK_CEC_H
#define _MTK_CEC_H
#include <linux/types.h>
struct device;
void mtk_cec_set_hpd_event(struct device *dev,
void (*hotplug_event)(bool hpd, struct device *dev),
struct device *hdmi_dev);
bool mtk_cec_hpd_high(struct device *dev);
#endif /* _MTK_CEC_H */
This diff is collapsed.
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MTK_HDMI_CTRL_H
#define _MTK_HDMI_CTRL_H
struct platform_driver;
extern struct platform_driver mtk_cec_driver;
extern struct platform_driver mtk_hdmi_ddc_driver;
extern struct platform_driver mtk_hdmi_phy_driver;
#endif /* _MTK_HDMI_CTRL_H */
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/time.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#define SIF1_CLOK (288)
#define DDC_DDCMCTL0 (0x0)
#define DDCM_ODRAIN BIT(31)
#define DDCM_CLK_DIV_OFFSET (16)
#define DDCM_CLK_DIV_MASK (0xfff << 16)
#define DDCM_CS_STATUS BIT(4)
#define DDCM_SCL_STATE BIT(3)
#define DDCM_SDA_STATE BIT(2)
#define DDCM_SM0EN BIT(1)
#define DDCM_SCL_STRECH BIT(0)
#define DDC_DDCMCTL1 (0x4)
#define DDCM_ACK_OFFSET (16)
#define DDCM_ACK_MASK (0xff << 16)
#define DDCM_PGLEN_OFFSET (8)
#define DDCM_PGLEN_MASK (0x7 << 8)
#define DDCM_SIF_MODE_OFFSET (4)
#define DDCM_SIF_MODE_MASK (0x7 << 4)
#define DDCM_START (0x1)
#define DDCM_WRITE_DATA (0x2)
#define DDCM_STOP (0x3)
#define DDCM_READ_DATA_NO_ACK (0x4)
#define DDCM_READ_DATA_ACK (0x5)
#define DDCM_TRI BIT(0)
#define DDC_DDCMD0 (0x8)
#define DDCM_DATA3 (0xff << 24)
#define DDCM_DATA2 (0xff << 16)
#define DDCM_DATA1 (0xff << 8)
#define DDCM_DATA0 (0xff << 0)
#define DDC_DDCMD1 (0xc)
#define DDCM_DATA7 (0xff << 24)
#define DDCM_DATA6 (0xff << 16)
#define DDCM_DATA5 (0xff << 8)
#define DDCM_DATA4 (0xff << 0)
struct mtk_hdmi_ddc {
struct i2c_adapter adap;
struct clk *clk;
void __iomem *regs;
};
static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int val)
{
writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
}
static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int val)
{
writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
}
static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int val)
{
return (readl(ddc->regs + offset) & val) == val;
}
static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int mask, unsigned int shift,
unsigned int val)
{
unsigned int tmp;
tmp = readl(ddc->regs + offset);
tmp &= ~mask;
tmp |= (val << shift) & mask;
writel(tmp, ddc->regs + offset);
}
static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,
unsigned int offset, unsigned int mask,
unsigned int shift)
{
return (readl(ddc->regs + offset) & mask) >> shift;
}
static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)
{
u32 val;
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
DDCM_SIF_MODE_OFFSET, mode);
sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
(val & DDCM_TRI) != DDCM_TRI, 4, 20000);
}
static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
{
struct device *dev = ddc->adap.dev.parent;
u32 remain_count, ack_count, ack_final, read_count, temp_count;
u32 index = 0;
u32 ack;
int i;
ddcm_trigger_mode(ddc, DDCM_START);
sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
0x00);
ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
dev_dbg(dev, "ack = 0x%x\n", ack);
if (ack != 0x01) {
dev_err(dev, "i2c ack err!\n");
return -ENXIO;
}
remain_count = msg->len;
ack_count = (msg->len - 1) / 8;
ack_final = 0;
while (remain_count > 0) {
if (ack_count > 0) {
read_count = 8;
ack_final = 0;
ack_count--;
} else {
read_count = remain_count;
ack_final = 1;
}
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
DDCM_PGLEN_OFFSET, read_count - 1);
ddcm_trigger_mode(ddc, (ack_final == 1) ?
DDCM_READ_DATA_NO_ACK :
DDCM_READ_DATA_ACK);
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
DDCM_ACK_OFFSET);
temp_count = 0;
while (((ack & (1 << temp_count)) != 0) && (temp_count < 8))
temp_count++;
if (((ack_final == 1) && (temp_count != (read_count - 1))) ||
((ack_final == 0) && (temp_count != read_count))) {
dev_err(dev, "Address NACK! ACK(0x%x)\n", ack);
break;
}
for (i = read_count; i >= 1; i--) {
int shift;
int offset;
if (i > 4) {
offset = DDC_DDCMD1;
shift = (i - 5) * 8;
} else {
offset = DDC_DDCMD0;
shift = (i - 1) * 8;
}
msg->buf[index + i - 1] = sif_read_mask(ddc, offset,
0xff << shift,
shift);
}
remain_count -= read_count;
index += read_count;
}
return 0;
}
static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
{
struct device *dev = ddc->adap.dev.parent;
u32 ack;
ddcm_trigger_mode(ddc, DDCM_START);
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
0x1);
ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
dev_dbg(dev, "ack = %d\n", ack);
if (ack != 0x03) {
dev_err(dev, "i2c ack err!\n");
return -EIO;
}
return 0;
}
static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter,
struct i2c_msg *msgs, int num)
{
struct mtk_hdmi_ddc *ddc = adapter->algo_data;
struct device *dev = adapter->dev.parent;
int ret;
int i;
if (!ddc) {
dev_err(dev, "invalid arguments\n");
return -EINVAL;
}
sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {
dev_err(dev, "ddc line is busy!\n");
return -EBUSY;
}
sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,
DDCM_CLK_DIV_OFFSET, SIF1_CLOK);
for (i = 0; i < num; i++) {
struct i2c_msg *msg = &msgs[i];
dev_dbg(dev, "i2c msg, adr:0x%x, flags:%d, len :0x%x\n",
msg->addr, msg->flags, msg->len);
if (msg->flags & I2C_M_RD)
ret = mtk_hdmi_ddc_read_msg(ddc, msg);
else
ret = mtk_hdmi_ddc_write_msg(ddc, msg);
if (ret < 0)
goto xfer_end;
}
ddcm_trigger_mode(ddc, DDCM_STOP);
return i;
xfer_end:
ddcm_trigger_mode(ddc, DDCM_STOP);
dev_err(dev, "ddc failed!\n");
return ret;
}
static u32 mtk_hdmi_ddc_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm mtk_hdmi_ddc_algorithm = {
.master_xfer = mtk_hdmi_ddc_xfer,
.functionality = mtk_hdmi_ddc_func,
};
static int mtk_hdmi_ddc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_hdmi_ddc *ddc;
struct resource *mem;
int ret;
ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);
if (!ddc)
return -ENOMEM;
ddc->clk = devm_clk_get(dev, "ddc-i2c");
if (IS_ERR(ddc->clk)) {
dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk);
return PTR_ERR(ddc->clk);
}
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ddc->regs = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(ddc->regs))
return PTR_ERR(ddc->regs);
ret = clk_prepare_enable(ddc->clk);
if (ret) {
dev_err(dev, "enable ddc clk failed!\n");
return ret;
}
strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));
ddc->adap.owner = THIS_MODULE;
ddc->adap.class = I2C_CLASS_DDC;
ddc->adap.algo = &mtk_hdmi_ddc_algorithm;
ddc->adap.retries = 3;
ddc->adap.dev.of_node = dev->of_node;
ddc->adap.algo_data = ddc;
ddc->adap.dev.parent = &pdev->dev;
ret = i2c_add_adapter(&ddc->adap);
if (ret < 0) {
dev_err(dev, "failed to add bus to i2c core\n");
goto err_clk_disable;
}
platform_set_drvdata(pdev, ddc);
dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);
dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);
dev_dbg(dev, "physical adr: %pa, end: %pa\n", &mem->start,
&mem->end);
return 0;
err_clk_disable:
clk_disable_unprepare(ddc->clk);
return ret;
}
static int mtk_hdmi_ddc_remove(struct platform_device *pdev)
{
struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);
i2c_del_adapter(&ddc->adap);
clk_disable_unprepare(ddc->clk);
return 0;
}
static const struct of_device_id mtk_hdmi_ddc_match[] = {
{ .compatible = "mediatek,mt8173-hdmi-ddc", },
{},
};
struct platform_driver mtk_hdmi_ddc_driver = {
.probe = mtk_hdmi_ddc_probe,
.remove = mtk_hdmi_ddc_remove,
.driver = {
.name = "mediatek-hdmi-ddc",
.of_match_table = mtk_hdmi_ddc_match,
},
};
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
MODULE_LICENSE("GPL v2");
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MTK_HDMI_REGS_H
#define _MTK_HDMI_REGS_H
#define GRL_INT_MASK 0x18
#define GRL_IFM_PORT 0x188
#define GRL_CH_SWAP 0x198
#define LR_SWAP BIT(0)
#define LFE_CC_SWAP BIT(1)
#define LSRS_SWAP BIT(2)
#define RLS_RRS_SWAP BIT(3)
#define LR_STATUS_SWAP BIT(4)
#define GRL_I2S_C_STA0 0x140
#define GRL_I2S_C_STA1 0x144
#define GRL_I2S_C_STA2 0x148
#define GRL_I2S_C_STA3 0x14C
#define GRL_I2S_C_STA4 0x150
#define GRL_I2S_UV 0x154
#define I2S_UV_V BIT(0)
#define I2S_UV_U BIT(1)
#define I2S_UV_CH_EN_MASK 0x3c
#define I2S_UV_CH_EN(x) BIT((x) + 2)
#define I2S_UV_TMDS_DEBUG BIT(6)
#define I2S_UV_NORMAL_INFO_INV BIT(7)
#define GRL_ACP_ISRC_CTRL 0x158
#define VS_EN BIT(0)
#define ACP_EN BIT(1)
#define ISRC1_EN BIT(2)
#define ISRC2_EN BIT(3)
#define GAMUT_EN BIT(4)
#define GRL_CTS_CTRL 0x160
#define CTS_CTRL_SOFT BIT(0)
#define GRL_INT 0x14
#define INT_MDI BIT(0)
#define INT_HDCP BIT(1)
#define INT_FIFO_O BIT(2)
#define INT_FIFO_U BIT(3)
#define INT_IFM_ERR BIT(4)
#define INT_INF_DONE BIT(5)
#define INT_NCTS_DONE BIT(6)
#define INT_CTRL_PKT_DONE BIT(7)
#define GRL_INT_MASK 0x18
#define GRL_CTRL 0x1C
#define CTRL_GEN_EN BIT(2)
#define CTRL_SPD_EN BIT(3)
#define CTRL_MPEG_EN BIT(4)
#define CTRL_AUDIO_EN BIT(5)
#define CTRL_AVI_EN BIT(6)
#define CTRL_AVMUTE BIT(7)
#define GRL_STATUS 0x20
#define STATUS_HTPLG BIT(0)
#define STATUS_PORD BIT(1)
#define GRL_DIVN 0x170
#define NCTS_WRI_ANYTIME BIT(6)
#define GRL_AUDIO_CFG 0x17C
#define AUDIO_ZERO BIT(0)
#define HIGH_BIT_RATE BIT(1)
#define SACD_DST BIT(2)
#define DST_NORMAL_DOUBLE BIT(3)
#define DSD_INV BIT(4)
#define LR_INV BIT(5)
#define LR_MIX BIT(6)
#define DSD_SEL BIT(7)
#define GRL_NCTS 0x184
#define GRL_CH_SW0 0x18C
#define GRL_CH_SW1 0x190
#define GRL_CH_SW2 0x194
#define CH_SWITCH(from, to) ((from) << ((to) * 3))
#define GRL_INFOFRM_VER 0x19C
#define GRL_INFOFRM_TYPE 0x1A0
#define GRL_INFOFRM_LNG 0x1A4
#define GRL_MIX_CTRL 0x1B4
#define MIX_CTRL_SRC_EN BIT(0)
#define BYPASS_VOLUME BIT(1)
#define MIX_CTRL_FLAT BIT(7)
#define GRL_AOUT_CFG 0x1C4
#define AOUT_BNUM_SEL_MASK 0x03
#define AOUT_24BIT 0x00
#define AOUT_20BIT 0x02
#define AOUT_16BIT 0x03
#define AOUT_FIFO_ADAP_CTRL BIT(6)
#define AOUT_BURST_PREAMBLE_EN BIT(7)
#define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \
AOUT_FIFO_ADAP_CTRL)
#define GRL_SHIFT_L1 0x1C0
#define GRL_SHIFT_R2 0x1B0
#define AUDIO_PACKET_OFF BIT(6)
#define GRL_CFG0 0x24
#define CFG0_I2S_MODE_MASK 0x3
#define CFG0_I2S_MODE_RTJ 0x1
#define CFG0_I2S_MODE_LTJ 0x0
#define CFG0_I2S_MODE_I2S 0x2
#define CFG0_W_LENGTH_MASK 0x30
#define CFG0_W_LENGTH_24BIT 0x00
#define CFG0_W_LENGTH_16BIT 0x10
#define GRL_CFG1 0x28
#define CFG1_EDG_SEL BIT(0)
#define CFG1_SPDIF BIT(1)
#define CFG1_DVI BIT(2)
#define CFG1_HDCP_DEBUG BIT(3)
#define GRL_CFG2 0x2c
#define CFG2_MHL_DE_SEL BIT(3)
#define CFG2_MHL_FAKE_DE_SEL BIT(4)
#define CFG2_MHL_DATA_REMAP BIT(5)
#define CFG2_NOTICE_EN BIT(6)
#define CFG2_ACLK_INV BIT(7)
#define GRL_CFG3 0x30
#define CFG3_AES_KEY_INDEX_MASK 0x3f
#define CFG3_CONTROL_PACKET_DELAY BIT(6)
#define CFG3_KSV_LOAD_START BIT(7)
#define GRL_CFG4 0x34
#define CFG4_AES_KEY_LOAD BIT(4)
#define CFG4_AV_UNMUTE_EN BIT(5)
#define CFG4_AV_UNMUTE_SET BIT(6)
#define CFG4_MHL_MODE BIT(7)
#define GRL_CFG5 0x38
#define CFG5_CD_RATIO_MASK 0x8F
#define CFG5_FS128 (0x1 << 4)
#define CFG5_FS256 (0x2 << 4)
#define CFG5_FS384 (0x3 << 4)
#define CFG5_FS512 (0x4 << 4)
#define CFG5_FS768 (0x6 << 4)
#define DUMMY_304 0x304
#define CHMO_SEL (0x3 << 2)
#define CHM1_SEL (0x3 << 4)
#define CHM2_SEL (0x3 << 6)
#define AUDIO_I2S_NCTS_SEL BIT(1)
#define AUDIO_I2S_NCTS_SEL_64 (1 << 1)
#define AUDIO_I2S_NCTS_SEL_128 (0 << 1)
#define NEW_GCP_CTRL BIT(0)
#define NEW_GCP_CTRL_MERGE BIT(0)
#define GRL_L_STATUS_0 0x200
#define GRL_L_STATUS_1 0x204
#define GRL_L_STATUS_2 0x208
#define GRL_L_STATUS_3 0x20c
#define GRL_L_STATUS_4 0x210
#define GRL_L_STATUS_5 0x214
#define GRL_L_STATUS_6 0x218
#define GRL_L_STATUS_7 0x21c
#define GRL_L_STATUS_8 0x220
#define GRL_L_STATUS_9 0x224
#define GRL_L_STATUS_10 0x228
#define GRL_L_STATUS_11 0x22c
#define GRL_L_STATUS_12 0x230
#define GRL_L_STATUS_13 0x234
#define GRL_L_STATUS_14 0x238
#define GRL_L_STATUS_15 0x23c
#define GRL_L_STATUS_16 0x240
#define GRL_L_STATUS_17 0x244
#define GRL_L_STATUS_18 0x248
#define GRL_L_STATUS_19 0x24c
#define GRL_L_STATUS_20 0x250
#define GRL_L_STATUS_21 0x254
#define GRL_L_STATUS_22 0x258
#define GRL_L_STATUS_23 0x25c
#define GRL_R_STATUS_0 0x260
#define GRL_R_STATUS_1 0x264
#define GRL_R_STATUS_2 0x268
#define GRL_R_STATUS_3 0x26c
#define GRL_R_STATUS_4 0x270
#define GRL_R_STATUS_5 0x274
#define GRL_R_STATUS_6 0x278
#define GRL_R_STATUS_7 0x27c
#define GRL_R_STATUS_8 0x280
#define GRL_R_STATUS_9 0x284
#define GRL_R_STATUS_10 0x288
#define GRL_R_STATUS_11 0x28c
#define GRL_R_STATUS_12 0x290
#define GRL_R_STATUS_13 0x294
#define GRL_R_STATUS_14 0x298
#define GRL_R_STATUS_15 0x29c
#define GRL_R_STATUS_16 0x2a0
#define GRL_R_STATUS_17 0x2a4
#define GRL_R_STATUS_18 0x2a8
#define GRL_R_STATUS_19 0x2ac
#define GRL_R_STATUS_20 0x2b0
#define GRL_R_STATUS_21 0x2b4
#define GRL_R_STATUS_22 0x2b8
#define GRL_R_STATUS_23 0x2bc
#define GRL_ABIST_CTRL0 0x2D4
#define GRL_ABIST_CTRL1 0x2D8
#define ABIST_EN BIT(7)
#define ABIST_DATA_FMT (0x7 << 0)
#define VIDEO_CFG_0 0x380
#define VIDEO_CFG_1 0x384
#define VIDEO_CFG_2 0x388
#define VIDEO_CFG_3 0x38c
#define VIDEO_CFG_4 0x390
#define VIDEO_SOURCE_SEL BIT(7)
#define NORMAL_PATH (1 << 7)
#define GEN_RGB (0 << 7)
#define HDMI_SYS_CFG1C 0x000
#define HDMI_ON BIT(0)
#define HDMI_RST BIT(1)
#define ANLG_ON BIT(2)
#define CFG10_DVI BIT(3)
#define HDMI_TST BIT(3)
#define SYS_KEYMASK1 (0xff << 8)
#define SYS_KEYMASK2 (0xff << 16)
#define AUD_OUTSYNC_EN BIT(24)
#define AUD_OUTSYNC_PRE_EN BIT(25)
#define I2CM_ON BIT(26)
#define E2PROM_TYPE_8BIT BIT(27)
#define MCM_E2PROM_ON BIT(28)
#define EXT_E2PROM_ON BIT(29)
#define HTPLG_PIN_SEL_OFF BIT(30)
#define AES_EFUSE_ENABLE BIT(31)
#define HDMI_SYS_CFG20 0x004
#define DEEP_COLOR_MODE_MASK (3 << 1)
#define COLOR_8BIT_MODE (0 << 1)
#define COLOR_10BIT_MODE (1 << 1)
#define COLOR_12BIT_MODE (2 << 1)
#define COLOR_16BIT_MODE (3 << 1)
#define DEEP_COLOR_EN BIT(0)
#define HDMI_AUDIO_TEST_SEL BIT(8)
#define HDMI2P0_EN BIT(11)
#define HDMI_OUT_FIFO_EN BIT(16)
#define HDMI_OUT_FIFO_CLK_INV BIT(17)
#define MHL_MODE_ON BIT(28)
#define MHL_PP_MODE BIT(29)
#define MHL_SYNC_AUTO_EN BIT(30)
#define HDMI_PCLK_FREE_RUN BIT(31)
#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
#endif
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