Commit 2a369ae0 authored by David S. Miller's avatar David S. Miller

Merge branch 'net-ll_temac-x86_64-support'

Esben Haabendal says:

====================
net: ll_temac: x86_64 support

This patch series adds support for use of ll_temac driver with
platform_data configuration and fixes endianess and 64-bit problems so
that it can be used on x86_64 platform.

A few bugfixes are also included.

Changes since v2:
  - Fixed lp->indirect_mutex initialization regression for OF
    platforms introduced in v2

Changes since v1:
  - Make indirect_mutex specification mandatory when using platform_data
  - Move header to include/linux/platform_data
  - Enable COMPILE_TEST for XILINX_LL_TEMAC
  - Rebased to v5.1-rc7
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ac97a359 73f7375d
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
config NET_VENDOR_XILINX config NET_VENDOR_XILINX
bool "Xilinx devices" bool "Xilinx devices"
default y default y
depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS || X86 || COMPILE_TEST
---help--- ---help---
If you have a network (Ethernet) card belonging to this class, say Y. If you have a network (Ethernet) card belonging to this class, say Y.
...@@ -33,8 +33,7 @@ config XILINX_AXI_EMAC ...@@ -33,8 +33,7 @@ config XILINX_AXI_EMAC
config XILINX_LL_TEMAC config XILINX_LL_TEMAC
tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver" tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
depends on (PPC || MICROBLAZE) depends on PPC || MICROBLAZE || X86 || COMPILE_TEST
depends on !64BIT || BROKEN
select PHYLIB select PHYLIB
---help--- ---help---
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
......
...@@ -334,6 +334,9 @@ struct temac_local { ...@@ -334,6 +334,9 @@ struct temac_local {
/* Connection to PHY device */ /* Connection to PHY device */
struct device_node *phy_node; struct device_node *phy_node;
/* For non-device-tree devices */
char phy_name[MII_BUS_ID_SIZE + 3];
phy_interface_t phy_interface;
/* MDIO bus data */ /* MDIO bus data */
struct mii_bus *mii_bus; /* MII bus reference */ struct mii_bus *mii_bus; /* MII bus reference */
...@@ -344,8 +347,10 @@ struct temac_local { ...@@ -344,8 +347,10 @@ struct temac_local {
#ifdef CONFIG_PPC_DCR #ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs; dcr_host_t sdma_dcrs;
#endif #endif
u32 (*dma_in)(struct temac_local *, int); u32 (*temac_ior)(struct temac_local *lp, int offset);
void (*dma_out)(struct temac_local *, int, u32); void (*temac_iow)(struct temac_local *lp, int offset, u32 value);
u32 (*dma_in)(struct temac_local *lp, int reg);
void (*dma_out)(struct temac_local *lp, int reg, u32 value);
int tx_irq; int tx_irq;
int rx_irq; int rx_irq;
...@@ -353,7 +358,10 @@ struct temac_local { ...@@ -353,7 +358,10 @@ struct temac_local {
struct sk_buff **rx_skb; struct sk_buff **rx_skb;
spinlock_t rx_lock; spinlock_t rx_lock;
struct mutex indirect_mutex; /* For synchronization of indirect register access. Must be
* shared mutex between interfaces in same TEMAC block.
*/
struct mutex *indirect_mutex;
u32 options; /* Current options word */ u32 options; /* Current options word */
int last_link; int last_link;
unsigned int temac_features; unsigned int temac_features;
...@@ -367,18 +375,24 @@ struct temac_local { ...@@ -367,18 +375,24 @@ struct temac_local {
int tx_bd_next; int tx_bd_next;
int tx_bd_tail; int tx_bd_tail;
int rx_bd_ci; int rx_bd_ci;
/* DMA channel control setup */
u32 tx_chnl_ctrl;
u32 rx_chnl_ctrl;
}; };
/* Wrappers for temac_ior()/temac_iow() function pointers above */
#define temac_ior(lp, o) ((lp)->temac_ior(lp, o))
#define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v))
/* xilinx_temac.c */ /* xilinx_temac.c */
u32 temac_ior(struct temac_local *lp, int offset);
void temac_iow(struct temac_local *lp, int offset, u32 value);
int temac_indirect_busywait(struct temac_local *lp); int temac_indirect_busywait(struct temac_local *lp);
u32 temac_indirect_in32(struct temac_local *lp, int reg); u32 temac_indirect_in32(struct temac_local *lp, int reg);
void temac_indirect_out32(struct temac_local *lp, int reg, u32 value); void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
/* xilinx_temac_mdio.c */ /* xilinx_temac_mdio.c */
int temac_mdio_setup(struct temac_local *lp, struct device_node *np); int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev);
void temac_mdio_teardown(struct temac_local *lp); void temac_mdio_teardown(struct temac_local *lp);
#endif /* XILINX_LL_TEMAC_H */ #endif /* XILINX_LL_TEMAC_H */
This diff is collapsed.
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/of_mdio.h> #include <linux/of_mdio.h>
#include <linux/platform_data/xilinx-ll-temac.h>
#include "ll_temac.h" #include "ll_temac.h"
...@@ -28,10 +29,10 @@ static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg) ...@@ -28,10 +29,10 @@ static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
/* Write the PHY address to the MIIM Access Initiator register. /* Write the PHY address to the MIIM Access Initiator register.
* When the transfer completes, the PHY register value will appear * When the transfer completes, the PHY register value will appear
* in the LSW0 register */ * in the LSW0 register */
mutex_lock(&lp->indirect_mutex); mutex_lock(lp->indirect_mutex);
temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg); temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
rc = temac_indirect_in32(lp, XTE_MIIMAI_OFFSET); rc = temac_indirect_in32(lp, XTE_MIIMAI_OFFSET);
mutex_unlock(&lp->indirect_mutex); mutex_unlock(lp->indirect_mutex);
dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n", dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n",
phy_id, reg, rc); phy_id, reg, rc);
...@@ -49,25 +50,34 @@ static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) ...@@ -49,25 +50,34 @@ static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
/* First write the desired value into the write data register /* First write the desired value into the write data register
* and then write the address into the access initiator register * and then write the address into the access initiator register
*/ */
mutex_lock(&lp->indirect_mutex); mutex_lock(lp->indirect_mutex);
temac_indirect_out32(lp, XTE_MGTDR_OFFSET, val); temac_indirect_out32(lp, XTE_MGTDR_OFFSET, val);
temac_indirect_out32(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg); temac_indirect_out32(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg);
mutex_unlock(&lp->indirect_mutex); mutex_unlock(lp->indirect_mutex);
return 0; return 0;
} }
int temac_mdio_setup(struct temac_local *lp, struct device_node *np) int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev)
{ {
struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct device_node *np = dev_of_node(&pdev->dev);
struct mii_bus *bus; struct mii_bus *bus;
u32 bus_hz; u32 bus_hz;
int clk_div; int clk_div;
int rc; int rc;
struct resource res; struct resource res;
/* Get MDIO bus frequency (if specified) */
bus_hz = 0;
if (np)
of_property_read_u32(np, "clock-frequency", &bus_hz);
else if (pdata)
bus_hz = pdata->mdio_clk_freq;
/* Calculate a reasonable divisor for the clock rate */ /* Calculate a reasonable divisor for the clock rate */
clk_div = 0x3f; /* worst-case default setting */ clk_div = 0x3f; /* worst-case default setting */
if (of_property_read_u32(np, "clock-frequency", &bus_hz) == 0) { if (bus_hz != 0) {
clk_div = bus_hz / (2500 * 1000 * 2) - 1; clk_div = bus_hz / (2500 * 1000 * 2) - 1;
if (clk_div < 1) if (clk_div < 1)
clk_div = 1; clk_div = 1;
...@@ -77,17 +87,23 @@ int temac_mdio_setup(struct temac_local *lp, struct device_node *np) ...@@ -77,17 +87,23 @@ int temac_mdio_setup(struct temac_local *lp, struct device_node *np)
/* Enable the MDIO bus by asserting the enable bit and writing /* Enable the MDIO bus by asserting the enable bit and writing
* in the clock config */ * in the clock config */
mutex_lock(&lp->indirect_mutex); mutex_lock(lp->indirect_mutex);
temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div); temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
mutex_unlock(&lp->indirect_mutex); mutex_unlock(lp->indirect_mutex);
bus = mdiobus_alloc(); bus = devm_mdiobus_alloc(&pdev->dev);
if (!bus) if (!bus)
return -ENOMEM; return -ENOMEM;
of_address_to_resource(np, 0, &res); if (np) {
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", of_address_to_resource(np, 0, &res);
(unsigned long long)res.start); snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
(unsigned long long)res.start);
} else if (pdata && pdata->mdio_bus_id >= 0) {
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
pdata->mdio_bus_id);
}
bus->priv = lp; bus->priv = lp;
bus->name = "Xilinx TEMAC MDIO"; bus->name = "Xilinx TEMAC MDIO";
bus->read = temac_mdio_read; bus->read = temac_mdio_read;
...@@ -98,23 +114,16 @@ int temac_mdio_setup(struct temac_local *lp, struct device_node *np) ...@@ -98,23 +114,16 @@ int temac_mdio_setup(struct temac_local *lp, struct device_node *np)
rc = of_mdiobus_register(bus, np); rc = of_mdiobus_register(bus, np);
if (rc) if (rc)
goto err_register; return rc;
mutex_lock(&lp->indirect_mutex); mutex_lock(lp->indirect_mutex);
dev_dbg(lp->dev, "MDIO bus registered; MC:%x\n", dev_dbg(lp->dev, "MDIO bus registered; MC:%x\n",
temac_indirect_in32(lp, XTE_MC_OFFSET)); temac_indirect_in32(lp, XTE_MC_OFFSET));
mutex_unlock(&lp->indirect_mutex); mutex_unlock(lp->indirect_mutex);
return 0; return 0;
err_register:
mdiobus_free(bus);
return rc;
} }
void temac_mdio_teardown(struct temac_local *lp) void temac_mdio_teardown(struct temac_local *lp)
{ {
mdiobus_unregister(lp->mii_bus); mdiobus_unregister(lp->mii_bus);
mdiobus_free(lp->mii_bus);
lp->mii_bus = NULL;
} }
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_XILINX_LL_TEMAC_H
#define __LINUX_XILINX_LL_TEMAC_H
#include <linux/if_ether.h>
#include <linux/phy.h>
struct ll_temac_platform_data {
bool txcsum; /* Enable/disable TX checksum */
bool rxcsum; /* Enable/disable RX checksum */
u8 mac_addr[ETH_ALEN]; /* MAC address (6 bytes) */
/* Clock frequency for input to MDIO clock generator */
u32 mdio_clk_freq;
unsigned long long mdio_bus_id; /* Unique id for MDIO bus */
int phy_addr; /* Address of the PHY to connect to */
phy_interface_t phy_interface; /* PHY interface mode */
bool reg_little_endian; /* Little endian TEMAC register access */
bool dma_little_endian; /* Little endian DMA register access */
/* Pre-initialized mutex to use for synchronizing indirect
* register access. When using both interfaces of a single
* TEMAC IP block, the same mutex should be passed here, as
* they share the same DCR bus bridge.
*/
struct mutex *indirect_mutex;
/* DMA channel control setup */
u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */
u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */
u8 rx_irq_timeout; /* RX Interrupt Delay Time-out */
u8 rx_irq_count; /* RX Interrupt Coalescing Threshold Count */
};
#endif /* __LINUX_XILINX_LL_TEMAC_H */
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