Commit 2a6f0614 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Olof Johansson

ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source

This clock will be used in audio subsystem. Since audio cannot work
without PLL we should indicate this.
Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 5c15bd28
......@@ -301,6 +301,7 @@ void __init clps711x_timer_init(void)
cpu = ext;
bus = cpu;
spi = 135400;
pll = 0;
} else {
cpu = pll;
if (cpu >= 36864000)
......
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