drm/i915/adl_p: Add stride restriction when using DPT

Alderlake-P have a new stride restriction when using DPT and it is used
by non linear framebuffers. Stride needs to be a power of two to take
full DPT rows, but stride is a parameter set by userspace.

What we could do is use a fake stride when doing DPT allocation so
HW requirements are met and userspace don't need to be changed to
met this power of two restrictions but this change will take a while
to be implemented so for now adding this restriction in driver to
reject atomic commits that would cause visual corruptions.

BSpec: 53393
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-8-imre.deak@intel.com

drivers/gpu/drm/i915/display/intel_display.c

@@ -11580,6 +11580,15 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			}
 		}
 
+		if (IS_ALDERLAKE_P(dev_priv) &&
+		    mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
+		    !is_power_of_2(mode_cmd->pitches[i])) {
+			drm_dbg_kms(&dev_priv->drm,
+				    "plane %d pitch (%d) must be power of two for tiled buffers\n",
+				    i, mode_cmd->pitches[i]);
+			goto err;
+		}
+
 		fb->obj[i] = &obj->base;
 	}