Commit 2c7f9a4d authored by Colin Xu's avatar Colin Xu Committed by Zhenyu Wang

drm/i915/gvt: Use consist max display pipe numbers as i915 definition

GVT implements a homogeneous vGPU as host GPU so max vGPU display pipes
can't exceed HW. The inconsistency definition has potential risks which
could cause array indexing overflow.

Remove the unnecessary define of INTEL_GVT_MAX_PIPE and align with i915.
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarColin Xu <colin.xu@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 39c68e87
...@@ -111,11 +111,9 @@ struct intel_vgpu_cfg_space { ...@@ -111,11 +111,9 @@ struct intel_vgpu_cfg_space {
#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
#define INTEL_GVT_MAX_PIPE 4
struct intel_vgpu_irq { struct intel_vgpu_irq {
bool irq_warn_once[INTEL_GVT_EVENT_MAX]; bool irq_warn_once[INTEL_GVT_EVENT_MAX];
DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
INTEL_GVT_EVENT_MAX); INTEL_GVT_EVENT_MAX);
}; };
......
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