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Commit 2d62aab5 authored by Andrew Davis's avatar Andrew Davis Committed by Nishanth Menon
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ARM: dts: keystone: Do not capitalize hex digits 

Signed-off-by: default avatarAndrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515183515.509371-5-afd@ti.comSigned-off-by: default avatarNishanth Menon <nm@ti.com>
parent 4b349837
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Showing with 27 additions and 27 deletions
arch/arm/boot/dts/keystone-k2e-evm.dts
View file @ 2d62aab5
...@@ -130,7 +130,7 @@ partition@100000 { ...@@ -130,7 +130,7 @@ partition@100000 {
partition@180000 { partition@180000 {
label = "ubifs"; label = "ubifs";
reg = <0x180000 0x1FE80000>; reg = <0x180000 0x1fe80000>;
}; };
}; };
}; };
......
arch/arm/boot/dts/keystone-k2e-netcp.dtsi
View file @ 2d62aab5
...@@ -167,7 +167,7 @@ cpts_refclk_mux: cpts-refclk-mux { ...@@ -167,7 +167,7 @@ cpts_refclk_mux: cpts-refclk-mux {
<&tsipclka>, <&tsrefclk>, <&tsipclka>, <&tsrefclk>,
<&tsipclkb>; <&tsipclkb>;
ti,mux-tbl = <0x0>, <0x1>, <0x2>, ti,mux-tbl = <0x0>, <0x1>, <0x2>,
<0x3>, <0x4>, <0x8>, <0xC>; <0x3>, <0x4>, <0x8>, <0xc>;
assigned-clocks = <&cpts_refclk_mux>; assigned-clocks = <&cpts_refclk_mux>;
assigned-clock-parents = <&chipclk12>; assigned-clock-parents = <&chipclk12>;
}; };
......
arch/arm/boot/dts/keystone-k2g-evm.dts
View file @ 2d62aab5
...@@ -218,16 +218,16 @@ K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3. ...@@ -218,16 +218,16 @@ K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.
emac_pins: emac-pins { emac_pins: emac-pins {
pinctrl-single,pins = < pinctrl-single,pins = <
K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
>; >;
...@@ -235,7 +235,7 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R ...@@ -235,7 +235,7 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R
mdio_pins: mdio-pins { mdio_pins: mdio-pins {
pinctrl-single,pins = < pinctrl-single,pins = <
K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
>; >;
}; };
...@@ -424,11 +424,11 @@ partition@3 { ...@@ -424,11 +424,11 @@ partition@3 {
}; };
partition@4 { partition@4 {
label = "QSPI.kernel"; label = "QSPI.kernel";
reg = <0x001C0000 0x0800000>; reg = <0x001c0000 0x0800000>;
}; };
partition@5 { partition@5 {
label = "QSPI.file-system"; label = "QSPI.file-system";
reg = <0x009C0000 0x3640000>; reg = <0x009c0000 0x3640000>;
}; };
}; };
}; };
......
arch/arm/boot/dts/keystone-k2g-ice.dts
View file @ 2d62aab5
...@@ -239,15 +239,15 @@ K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0. ...@@ -239,15 +239,15 @@ K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.
mmc1_pins: mmc1-pins { mmc1_pins: mmc1-pins {
pinctrl-single,pins = < pinctrl-single,pins = <
K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */
K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */
K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ K2G_CORE_IOPAD(0x111c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */
>; >;
}; };
...@@ -285,16 +285,16 @@ K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.g ...@@ -285,16 +285,16 @@ K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.g
emac_pins: emac-pins { emac_pins: emac-pins {
pinctrl-single,pins = < pinctrl-single,pins = <
K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
>; >;
...@@ -302,7 +302,7 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R ...@@ -302,7 +302,7 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R
mdio_pins: mdio-pins { mdio_pins: mdio-pins {
pinctrl-single,pins = < pinctrl-single,pins = <
K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
>; >;
}; };
......
arch/arm/boot/dts/keystone-k2g.dtsi
View file @ 2d62aab5
...@@ -177,7 +177,7 @@ uart2: serial@2531400 { ...@@ -177,7 +177,7 @@ uart2: serial@2531400 {
dcan0: can@260b200 { dcan0: can@260b200 {
compatible = "ti,am4372-d_can", "ti,am3352-d_can"; compatible = "ti,am4372-d_can", "ti,am3352-d_can";
reg = <0x0260B200 0x200>; reg = <0x0260b200 0x200>;
interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
status = "disabled"; status = "disabled";
power-domains = <&k2g_pds 0x0008>; power-domains = <&k2g_pds 0x0008>;
...@@ -186,7 +186,7 @@ dcan0: can@260b200 { ...@@ -186,7 +186,7 @@ dcan0: can@260b200 {
dcan1: can@260b400 { dcan1: can@260b400 {
compatible = "ti,am4372-d_can", "ti,am3352-d_can"; compatible = "ti,am4372-d_can", "ti,am3352-d_can";
reg = <0x0260B400 0x200>; reg = <0x0260b400 0x200>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
status = "disabled"; status = "disabled";
power-domains = <&k2g_pds 0x0009>; power-domains = <&k2g_pds 0x0009>;
...@@ -593,7 +593,7 @@ spi1: spi@21805800 { ...@@ -593,7 +593,7 @@ spi1: spi@21805800 {
spi2: spi@21805c00 { spi2: spi@21805c00 {
compatible = "ti,keystone-spi"; compatible = "ti,keystone-spi";
reg = <0x21805C00 0x200>; reg = <0x21805c00 0x200>;
num-cs = <4>; num-cs = <4>;
ti,davinci-spi-intr-line = <0>; ti,davinci-spi-intr-line = <0>;
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
......
arch/arm/boot/dts/keystone-k2l-evm.dts
View file @ 2d62aab5
...@@ -103,7 +103,7 @@ partition@100000 { ...@@ -103,7 +103,7 @@ partition@100000 {
partition@180000 { partition@180000 {
label = "ubifs"; label = "ubifs";
reg = <0x180000 0x7FE80000>; reg = <0x180000 0x7fe80000>;
}; };
}; };
}; };
......
arch/arm/boot/dts/keystone-k2l.dtsi
View file @ 2d62aab5
...@@ -170,7 +170,7 @@ gpio_emu_pins: gpio-emu-pins { ...@@ -170,7 +170,7 @@ gpio_emu_pins: gpio-emu-pins {
* GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
* GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
*/ */
0x4 0x0000 0xFFFE0000 0x4 0x0000 0xfffe0000
>; >;
}; };
...@@ -190,7 +190,7 @@ gpio_timio_pins: gpio-timio-pins { ...@@ -190,7 +190,7 @@ gpio_timio_pins: gpio-timio-pins {
* GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
* GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
*/ */
0x4 0x0 0xFFF0 0x4 0x0 0xfff0
>; >;
}; };
...@@ -202,7 +202,7 @@ gpio_spi2cs_pins: gpio-spi2cs-pins { ...@@ -202,7 +202,7 @@ gpio_spi2cs_pins: gpio-spi2cs-pins {
* GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
* GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
*/ */
0x4 0x0 0xF 0x4 0x0 0xf
>; >;
}; };
...@@ -226,7 +226,7 @@ gpio_dfeio_pins: gpio-dfeio-pins { ...@@ -226,7 +226,7 @@ gpio_dfeio_pins: gpio-dfeio-pins {
* GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
* GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
*/ */
0x8 0x0 0xFFFF0000 0x8 0x0 0xffff0000
>; >;
}; };
...@@ -250,7 +250,7 @@ gpio_emifa_pins: gpio-emifa-pins { ...@@ -250,7 +250,7 @@ gpio_emifa_pins: gpio-emifa-pins {
* GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
* GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
*/ */
0x8 0x0 0xFFFF 0x8 0x0 0xffff
>; >;
}; };
}; };
......
arch/arm/boot/dts/keystone.dtsi
View file @ 2d62aab5
...@@ -282,7 +282,7 @@ gpio0: gpio@260bf00 { ...@@ -282,7 +282,7 @@ gpio0: gpio@260bf00 {
ti,davinci-gpio-unbanked = <32>; ti,davinci-gpio-unbanked = <32>;
}; };
aemif: aemif@21000A00 { aemif: aemif@21000a00 {
compatible = "ti,keystone-aemif", "ti,davinci-aemif"; compatible = "ti,keystone-aemif", "ti,davinci-aemif";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
...@@ -290,9 +290,9 @@ aemif: aemif@21000A00 { ...@@ -290,9 +290,9 @@ aemif: aemif@21000A00 {
clock-names = "aemif"; clock-names = "aemif";
clock-ranges; clock-ranges;
reg = <0x21000A00 0x00000100>; reg = <0x21000a00 0x00000100>;
ranges = <0 0 0x30000000 0x10000000 ranges = <0 0 0x30000000 0x10000000
1 0 0x21000A00 0x00000100>; 1 0 0x21000a00 0x00000100>;
}; };
pcie0: pcie@21800000 { pcie0: pcie@21800000 {
......
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