Commit 2e56ff20 authored by Kumar Gala's avatar Kumar Gala

[POWERPC] Make endianess of cfg_addr for indirect pci ops runtime

Make it so we do a runtime check to know if we need to write cfg_addr
as big or little endian.  This is needed if we want to allow 86xx support
to co-exist in the same kernel as other 6xx PPCs.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent d5269966
...@@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI ...@@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI
default y if 40x || 44x default y if 40x || 44x
default n default n
config PPC_INDIRECT_PCI_BE
bool
depends PPC_INDIRECT_PCI
default n
config EISA config EISA
bool bool
......
...@@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np) ...@@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np)
setup_indirect_pci(hose, setup_indirect_pci(hose,
r.start + offsetof(pci_cpm2_t, pci_cfg_addr), r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
r.start + offsetof(pci_cpm2_t, pci_cfg_data)); r.start + offsetof(pci_cpm2_t, pci_cfg_data),
0);
pci_process_bridge_OF_ranges(hose, np, 1); pci_process_bridge_OF_ranges(hose, np, 1);
} }
......
...@@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev) ...@@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
*/ */
/* PCI 1 */ /* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8500) { if ((rsrc.start & 0xfffff) == 0x8500) {
setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304); setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
} }
/* PCI 2 */ /* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x8600) { if ((rsrc.start & 0xfffff) == 0x8600) {
setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384); setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
primary = 0; primary = 0;
} }
......
...@@ -51,7 +51,6 @@ config MPC85xx ...@@ -51,7 +51,6 @@ config MPC85xx
bool bool
select PPC_UDBG_16550 select PPC_UDBG_16550
select PPC_INDIRECT_PCI if PCI select PPC_INDIRECT_PCI if PCI
select PPC_INDIRECT_PCI_BE if PCI
select MPIC select MPIC
select FSL_PCI if PCI select FSL_PCI if PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250 select SERIAL_8250_SHARE_IRQ if SERIAL_8250
......
...@@ -14,7 +14,6 @@ endchoice ...@@ -14,7 +14,6 @@ endchoice
config MPC8641 config MPC8641
bool bool
select PPC_INDIRECT_PCI_BE if PCI
select FSL_PCI if PCI select FSL_PCI if PCI
select PPC_UDBG_16550 select PPC_UDBG_16550
select MPIC select MPIC
......
...@@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev) ...@@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev)
} }
iounmap(reg); iounmap(reg);
setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
} }
/* Marvell Discovery II based Pegasos 2 */ /* Marvell Discovery II based Pegasos 2 */
...@@ -277,13 +277,14 @@ chrp_find_bridges(void) ...@@ -277,13 +277,14 @@ chrp_find_bridges(void)
hose->cfg_data = p; hose->cfg_data = p;
gg2_pci_config_base = p; gg2_pci_config_base = p;
} else if (is_pegasos == 1) { } else if (is_pegasos == 1) {
setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
} else if (is_pegasos == 2) { } else if (is_pegasos == 2) {
setup_peg2(hose, dev); setup_peg2(hose, dev);
} else if (!strncmp(model, "IBM,CPC710", 10)) { } else if (!strncmp(model, "IBM,CPC710", 10)) {
setup_indirect_pci(hose, setup_indirect_pci(hose,
r.start + 0x000f8000, r.start + 0x000f8000,
r.start + 0x000f8010); r.start + 0x000f8010,
0);
if (index == 0) { if (index == 0) {
dma = of_get_property(dev, "system-dma-base", dma = of_get_property(dev, "system-dma-base",
&len); &len);
......
...@@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev) ...@@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev)
return -ENOMEM; return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0; hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff; hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, 0xfec00000, 0xfee00000); setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
/* Interpret the "ranges" property */ /* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */ /* This also maps the I/O region and sets isa_io/mem_base */
......
...@@ -185,7 +185,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) ...@@ -185,7 +185,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff; hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
setup_pci_cmd(hose); setup_pci_cmd(hose);
/* check PCI express link status */ /* check PCI express link status */
......
...@@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) ...@@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
void __init setup_grackle(struct pci_controller *hose) void __init setup_grackle(struct pci_controller *hose)
{ {
setup_indirect_pci(hose, 0xfec00000, 0xfee00000); setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
if (machine_is_compatible("PowerMac1,1")) if (machine_is_compatible("PowerMac1,1"))
pci_assign_all_buses = 1; pci_assign_all_buses = 1;
if (machine_is_compatible("AAPL,PowerBook1998")) if (machine_is_compatible("AAPL,PowerBook1998"))
......
...@@ -20,12 +20,6 @@ ...@@ -20,12 +20,6 @@
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#ifdef CONFIG_PPC_INDIRECT_PCI_BE
#define PCI_CFG_OUT out_be32
#else
#define PCI_CFG_OUT out_le32
#endif
static int static int
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val) int len, u32 *val)
...@@ -58,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, ...@@ -58,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
else else
reg = offset & 0xfc; reg = offset & 0xfc;
PCI_CFG_OUT(hose->cfg_addr, if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
(0x80000000 | (bus_no << 16) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
| (devfn << 8) | reg | cfg_type)); (devfn << 8) | reg | cfg_type));
else
out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
(devfn << 8) | reg | cfg_type));
/* /*
* Note: the caller has already checked that offset is * Note: the caller has already checked that offset is
...@@ -113,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, ...@@ -113,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
else else
reg = offset & 0xfc; reg = offset & 0xfc;
PCI_CFG_OUT(hose->cfg_addr, if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
(0x80000000 | (bus_no << 16) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
| (devfn << 8) | reg | cfg_type)); (devfn << 8) | reg | cfg_type));
else
out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
(devfn << 8) | reg | cfg_type));
/* surpress setting of PCI_PRIMARY_BUS */ /* surpress setting of PCI_PRIMARY_BUS */
if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
...@@ -149,7 +149,7 @@ static struct pci_ops indirect_pci_ops = ...@@ -149,7 +149,7 @@ static struct pci_ops indirect_pci_ops =
}; };
void __init void __init
setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags)
{ {
unsigned long base = cfg_addr & PAGE_MASK; unsigned long base = cfg_addr & PAGE_MASK;
void __iomem *mbase; void __iomem *mbase;
......
...@@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev) ...@@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev)
hose->first_busno = bus_range ? bus_range[0] : 0; hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff; hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, rsrc.start, rsrc.start + 4); setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
hose->self_busno = hose->first_busno; hose->self_busno = hose->first_busno;
printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
......
...@@ -49,11 +49,13 @@ struct pci_controller { ...@@ -49,11 +49,13 @@ struct pci_controller {
* hanging if we don't have link and try to do config cycles to * hanging if we don't have link and try to do config cycles to
* anything but the PHB. Only allow talking to the PHB if this is * anything but the PHB. Only allow talking to the PHB if this is
* set. * set.
* BIG_ENDIAN - cfg_addr is a big endian register
*/ */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) #define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
u32 indirect_type; u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem /* Currently, we limit ourselves to 1 IO range and 3 mem
...@@ -88,7 +90,7 @@ extern int early_find_capability(struct pci_controller *hose, int bus, ...@@ -88,7 +90,7 @@ extern int early_find_capability(struct pci_controller *hose, int bus,
int dev_fn, int cap); int dev_fn, int cap);
extern void setup_indirect_pci(struct pci_controller* hose, extern void setup_indirect_pci(struct pci_controller* hose,
u32 cfg_addr, u32 cfg_data); u32 cfg_addr, u32 cfg_data, u32 flags);
extern void setup_grackle(struct pci_controller *hose); extern void setup_grackle(struct pci_controller *hose);
#else #else
......
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