drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache

There's no need to store all this stuff in intel_fbc_state_cache.
Just check it all against the plane/crtc states and store only
what we need. Probably more should get nuked still, but this
is a start.

So what we'll do is:
- each plane will check its own state and update its local
  no_fbc_reason
- the per-plane no_fbc_reason (if any) then gets propagated
  to the cache->no_fbc_reason while doing the actual update
- fbc->no_fbc_reason gets updated in the end with either
  the value from the cache or directly from frontbuffer
  tracking

It's still a bit messy, but should hopefuly get cleaned up
more in the future. At least now we can observe each plane's
reasons for rejecting FBC now more consistently, and we don't
have so mcuh redundant state store all over the place.

v2: store no_fbc_reason per-plane instead of per-pipe
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-4-ville.syrjala@linux.intel.comReviewed-by: Mika Kahola <mika.kahola@intel.com>

drivers/gpu/drm/i915/display/intel_display.c

@@ -8047,7 +8047,6 @@ static int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		goto fail;
 
-	intel_fbc_choose_crtc(dev_priv, state);
 	ret = intel_compute_global_watermarks(state);
 	if (ret)
 		goto fail;
@@ -8079,6 +8078,10 @@ static int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		goto fail;
 
+	ret = intel_fbc_atomic_check(state);
+	if (ret)
+		goto fail;
+
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		if (new_crtc_state->uapi.async_flip) {

drivers/gpu/drm/i915/display/intel_display_types.h

@@ -695,6 +695,8 @@ struct intel_plane_state {
 
 	/* Clear Color Value */
 	u64 ccval;
+
+	const char *no_fbc_reason;
 };
 
 struct intel_initial_plane_config {
@@ -1125,8 +1127,6 @@ struct intel_crtc_state {
 
 	bool crc_enabled;
 
-	bool enable_fbc;
-
 	bool double_wide;
 
 	int pbn;

drivers/gpu/drm/i915/display/intel_fbc.h

@@ -17,8 +17,7 @@ struct intel_crtc_state;
 struct intel_fbc;
 struct intel_plane_state;
 
-void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
-			   struct intel_atomic_state *state);
+int intel_fbc_atomic_check(struct intel_atomic_state *state);
 bool intel_fbc_is_active(struct intel_fbc *fbc);
 bool intel_fbc_is_compressing(struct intel_fbc *fbc);
 bool intel_fbc_pre_update(struct intel_atomic_state *state,

drivers/gpu/drm/i915/i915_drv.h

@@ -413,26 +413,11 @@ struct intel_fbc {
 	 * these problems.
 	 */
 	struct intel_fbc_state_cache {
-		struct {
-			unsigned int mode_flags;
-			u32 hsw_bdw_pixel_rate;
-		} crtc;
+		const char *no_fbc_reason;
 
 		struct {
-			unsigned int rotation;
 			int src_w;
 			int src_h;
-			bool visible;
-			/*
-			 * Display surface base address adjustement for
-			 * pageflips. Note that on gen4+ this only adjusts up
-			 * to a tile, offsets within a tile are handled in
-			 * the hw itself (with the TILEOFF register).
-			 */
-			int adjusted_x;
-			int adjusted_y;
-
-			u16 pixel_blend_mode;
 		} plane;
 
 		struct {
@@ -444,7 +429,6 @@ struct intel_fbc {
 		unsigned int fence_y_offset;
 		u16 interval;
 		s8 fence_id;
-		bool psr2_active;
 	} state_cache;
 
 	/*
@@ -456,7 +440,6 @@ struct intel_fbc {
 	 */
 	struct intel_fbc_reg_params {
 		struct {
-			enum pipe pipe;
 			enum i9xx_plane_id i9xx_plane;
 		} crtc;
 
@@ -472,7 +455,6 @@ struct intel_fbc {
 		u16 override_cfb_stride;
 		u16 interval;
 		s8 fence_id;
-		bool plane_visible;
 	} params;
 
 	const char *no_fbc_reason;