Port step some changes at authors request.

drivers/video/riva/riva_hw.c

@@ -1220,7 +1220,6 @@ static void CalcStateExt
             state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
             break;
         case NV_ARCH_10:
-	case NV_ARCH_20:
             nv10UpdateArbitrationSettings(VClk, 
                                           pixelDepth * 8, 
                                          &(state->arbitration0),
@@ -1286,7 +1285,6 @@ static void UpdateFifoState
             chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
             break;
         case NV_ARCH_10:
-	case NV_ARCH_20:
             /*
              * Initialize state for the RivaTriangle3D05 routines.
              */
@@ -1395,7 +1393,6 @@ static void LoadStateExt
             chip->PGRAPH[0x0000067C/4] = state->pitch3;
             break;
         case NV_ARCH_10:
-	case NV_ARCH_20:
             LOAD_FIXED_STATE(nv10,PFIFO);
             LOAD_FIXED_STATE(nv10,PRAMIN);
             LOAD_FIXED_STATE(nv10,PGRAPH);
@@ -1424,31 +1421,15 @@ static void LoadStateExt
                     chip->Tri03 = 0L;
                     break;
             }
-
-	    if (chip->Architecture == NV_ARCH_10) {	
-            	chip->PGRAPH[0x00000640/4] = state->offset0;
-            	chip->PGRAPH[0x00000644/4] = state->offset1;
-            	chip->PGRAPH[0x00000648/4] = state->offset2;
-            	chip->PGRAPH[0x0000064C/4] = state->offset3;
-            	chip->PGRAPH[0x00000670/4] = state->pitch0;
-            	chip->PGRAPH[0x00000674/4] = state->pitch1;
-            	chip->PGRAPH[0x00000678/4] = state->pitch2;
-            	chip->PGRAPH[0x0000067C/4] = state->pitch3;
-            	chip->PGRAPH[0x00000680/4] = state->pitch3;
-	    } else {
-		chip->PGRAPH[0x00000820/4] = state->offset0;
-		chip->PGRAPH[0x00000824/4] = state->offset1;
-		chip->PGRAPH[0x00000828/4] = state->offset2;
-		chip->PGRAPH[0x0000082C/4] = state->offset3;
-		chip->PGRAPH[0x00000850/4] = state->pitch0;
-		chip->PGRAPH[0x00000854/4] = state->pitch1;
-		chip->PGRAPH[0x00000858/4] = state->pitch2;
-		chip->PGRAPH[0x0000085C/4] = state->pitch3;
-		chip->PGRAPH[0x00000860/4] = state->pitch3;
-		chip->PGRAPH[0x00000864/4] = state->pitch3;
-		chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
-		chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
-	    }	
+            chip->PGRAPH[0x00000640/4] = state->offset0;
+            chip->PGRAPH[0x00000644/4] = state->offset1;
+            chip->PGRAPH[0x00000648/4] = state->offset2;
+            chip->PGRAPH[0x0000064C/4] = state->offset3;
+            chip->PGRAPH[0x00000670/4] = state->pitch0;
+            chip->PGRAPH[0x00000674/4] = state->pitch1;
+            chip->PGRAPH[0x00000678/4] = state->pitch2;
+            chip->PGRAPH[0x0000067C/4] = state->pitch3;
+            chip->PGRAPH[0x00000680/4] = state->pitch3;
             chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4];
             chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4];
             chip->PGRAPH[0x00000B08/4] = chip->PFB[0x00000248/4];
@@ -1626,7 +1607,6 @@ static void UnloadStateExt
             state->pitch3   = chip->PGRAPH[0x0000067C/4];
             break;
         case NV_ARCH_10:
-	case NV_ARCH_20:
             state->offset0  = chip->PGRAPH[0x00000640/4];
             state->offset1  = chip->PGRAPH[0x00000644/4];
             state->offset2  = chip->PGRAPH[0x00000648/4];

drivers/video/riva/riva_hw.h

@@ -74,8 +74,6 @@ typedef unsigned int   U032;
 #define NV_ARCH_03  0x03
 #define NV_ARCH_04  0x04
 #define NV_ARCH_10  0x10
-#define NV_ARCH_20  0x20
-
 /***************************************************************************\
 *                                                                           *
 *                             FIFO registers.                               *

drivers/video/riva/rivafb.h

@@ -3,7 +3,6 @@
 
 #include <linux/config.h>
 #include <linux/fb.h>
-#include <linux/timer.h>
 #include <video/fbcon.h>
 #include <video/fbcon-cfb4.h>
 #include <video/fbcon-cfb8.h>
@@ -28,35 +27,58 @@ struct riva_regs {
 	RIVA_HW_STATE ext;
 };
 
-#define MAX_CURS                32
-
-struct riva_cursor {
-        int enable;
-        int on;
-        int vbl_cnt;
-        int last_slice_moves, prev_slice_moves;
-        int blink_rate;
-        struct {
-                u16 x, y;
-        } pos, size;
-        unsigned short image[MAX_CURS*MAX_CURS];
-        struct timer_list *timer;
-};
+typedef struct {
+	unsigned char red, green, blue, transp;
+} riva_cfb8_cmap_t;
+
+struct rivafb_info;
+struct rivafb_info {
+	struct fb_info info;	/* kernel framebuffer info */
 
-/* describes the state of a Riva board */
-struct riva_par {
 	RIVA_HW_INST riva;	/* interface to riva_hw.c */
 
+	const char *drvr_name;	/* Riva hardware board type */
+
+	unsigned long ctrl_base_phys;	/* physical control register base addr */
+	unsigned long fb_base_phys;	/* physical framebuffer base addr */
+
+	caddr_t ctrl_base;	/* virtual control register base addr */
+	caddr_t fb_base;	/* virtual framebuffer base addr */
+
 	unsigned ram_amount;	/* amount of RAM on card, in bytes */
 	unsigned dclk_max;	/* max DCLK */
 
 	struct riva_regs initial_state;	/* initial startup video mode */
 	struct riva_regs current_state;
 
+	struct display disp;
+	int currcon;
+	struct display *currcon_display;
+
+	struct rivafb_info *next;
+
+	struct pci_dev *pd;	/* pointer to board's pci info */
+	unsigned base0_region_size;	/* size of control register region */
+	unsigned base1_region_size;	/* size of framebuffer region */
+
 	struct riva_cursor *cursor;
-        caddr_t ctrl_base;      /* Virtual control register base addr */
+
+	struct display_switch dispsw;
+
+	riva_cfb8_cmap_t palette[256];	/* VGA DAC palette cache */
+
+#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
+	union {
+#ifdef FBCON_HAS_CFB16
+		u_int16_t cfb16[16];
+#endif
+#ifdef FBCON_HAS_CFB32
+		u_int32_t cfb32[16];
+#endif
+	} con_cmap;
+#endif				/* FBCON_HAS_CFB16 | FBCON_HAS_CFB32 */
 #ifdef CONFIG_MTRR
-        struct { int vram; int vram_valid; } mtrr;
+	struct { int vram; int vram_valid; } mtrr;
 #endif
 };
 

drivers/video/sa1100fb.h

@@ -61,13 +61,13 @@ struct sa1100fb_lcd_reg {
 #define RGB_16	(1)
 #define NR_RGB	2
 
-struct sa1100_par {
+struct sa1100fb_info {
+	struct fb_info		fb;
 	struct sa1100fb_rgb	*rgb[NR_RGB];
 
+	u_int			max_bpp;
 	u_int			max_xres;
 	u_int			max_yres;
-	u_int			max_bpp;
-	u_int			bpp;
 
 	/*
 	 * These are the addresses we mapped
@@ -86,13 +86,12 @@ struct sa1100_par {
 	dma_addr_t		dbar1;
 	dma_addr_t		dbar2;
 
+	u_int			lccr0;
+	u_int			lccr3;
 	u_int			cmap_inverse:1,
 				cmap_static:1,
 				unused:30;
 
-	u_int			lccr0;
-	u_int			lccr3;
-
 	u_int			reg_lccr0;
 	u_int			reg_lccr1;
 	u_int			reg_lccr2;
@@ -103,14 +102,18 @@ struct sa1100_par {
 	struct semaphore	ctrlr_sem;
 	wait_queue_head_t	ctrlr_wait;
 	struct tq_struct	task;
+
 #ifdef CONFIG_PM
 	struct pm_dev		*pm;
 #endif
+#ifdef CONFIG_CPU_FREQ
+	struct notifier_block	clockchg;
+#endif
 };
 
 #define __type_entry(ptr,type,member) ((type *)((char *)(ptr)-offsetof(type,member)))
 
-#define TO_INF(ptr,member)	__type_entry(ptr, struct fb_info, member)
+#define TO_INF(ptr,member)	__type_entry(ptr,struct sa1100fb_info,member)
 
 #define SA1100_PALETTE_MODE_VAL(bpp)    (((bpp) & 0x018) << 9)