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Commit 2fd7db3c authored by Oded Gabbay's avatar Oded Gabbay
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habanalabs/gaudi2: update asic register files 

Update some register files with the latest h/w auto-generated files.
There is no functional change.
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent e2a079a2
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Showing with 114 additions and 155 deletions
drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h
View file @ 2fd7db3c
......@@ -7,93 +7,91 @@
#ifndef __GAUDI2_ARC_COMMON_PACKETS_H__
#define __GAUDI2_ARC_COMMON_PACKETS_H__
/*
* CPU IDs for each ARC CPUs
*/
#define CPU_ID_SCHED_ARC0 0 /* FARM_ARC0 */
#define CPU_ID_SCHED_ARC1 1 /* FARM_ARC1 */
#define CPU_ID_SCHED_ARC2 2 /* FARM_ARC2 */
#define CPU_ID_SCHED_ARC3 3 /* FARM_ARC3 */
/* Dcore1 MME Engine ARC instance used as scheduler */
#define CPU_ID_SCHED_ARC4 4 /* DCORE1_MME0 */
/* Dcore3 MME Engine ARC instance used as scheduler */
#define CPU_ID_SCHED_ARC5 5 /* DCORE3_MME0 */
enum {
CPU_ID_SCHED_ARC0 = 0, /* FARM_ARC0 */
CPU_ID_SCHED_ARC1 = 1, /* FARM_ARC1 */
CPU_ID_SCHED_ARC2 = 2, /* FARM_ARC2 */
CPU_ID_SCHED_ARC3 = 3, /* FARM_ARC3 */
/* Dcore1 MME Engine ARC instance used as scheduler */
CPU_ID_SCHED_ARC4 = 4, /* DCORE1_MME0 */
/* Dcore3 MME Engine ARC instance used as scheduler */
CPU_ID_SCHED_ARC5 = 5, /* DCORE3_MME0 */
#define CPU_ID_TPC_QMAN_ARC0 6 /* DCORE0_TPC0 */
#define CPU_ID_TPC_QMAN_ARC1 7 /* DCORE0_TPC1 */
#define CPU_ID_TPC_QMAN_ARC2 8 /* DCORE0_TPC2 */
#define CPU_ID_TPC_QMAN_ARC3 9 /* DCORE0_TPC3 */
#define CPU_ID_TPC_QMAN_ARC4 10 /* DCORE0_TPC4 */
#define CPU_ID_TPC_QMAN_ARC5 11 /* DCORE0_TPC5 */
#define CPU_ID_TPC_QMAN_ARC6 12 /* DCORE1_TPC0 */
#define CPU_ID_TPC_QMAN_ARC7 13 /* DCORE1_TPC1 */
#define CPU_ID_TPC_QMAN_ARC8 14 /* DCORE1_TPC2 */
#define CPU_ID_TPC_QMAN_ARC9 15 /* DCORE1_TPC3 */
#define CPU_ID_TPC_QMAN_ARC10 16 /* DCORE1_TPC4 */
#define CPU_ID_TPC_QMAN_ARC11 17 /* DCORE1_TPC5 */
#define CPU_ID_TPC_QMAN_ARC12 18 /* DCORE2_TPC0 */
#define CPU_ID_TPC_QMAN_ARC13 19 /* DCORE2_TPC1 */
#define CPU_ID_TPC_QMAN_ARC14 20 /* DCORE2_TPC2 */
#define CPU_ID_TPC_QMAN_ARC15 21 /* DCORE2_TPC3 */
#define CPU_ID_TPC_QMAN_ARC16 22 /* DCORE2_TPC4 */
#define CPU_ID_TPC_QMAN_ARC17 23 /* DCORE2_TPC5 */
#define CPU_ID_TPC_QMAN_ARC18 24 /* DCORE3_TPC0 */
#define CPU_ID_TPC_QMAN_ARC19 25 /* DCORE3_TPC1 */
#define CPU_ID_TPC_QMAN_ARC20 26 /* DCORE3_TPC2 */
#define CPU_ID_TPC_QMAN_ARC21 27 /* DCORE3_TPC3 */
#define CPU_ID_TPC_QMAN_ARC22 28 /* DCORE3_TPC4 */
#define CPU_ID_TPC_QMAN_ARC23 29 /* DCORE3_TPC5 */
#define CPU_ID_TPC_QMAN_ARC24 30 /* DCORE0_TPC6 - Never present */
CPU_ID_TPC_QMAN_ARC0 = 6, /* DCORE0_TPC0 */
CPU_ID_TPC_QMAN_ARC1 = 7, /* DCORE0_TPC1 */
CPU_ID_TPC_QMAN_ARC2 = 8, /* DCORE0_TPC2 */
CPU_ID_TPC_QMAN_ARC3 = 9, /* DCORE0_TPC3 */
CPU_ID_TPC_QMAN_ARC4 = 10, /* DCORE0_TPC4 */
CPU_ID_TPC_QMAN_ARC5 = 11, /* DCORE0_TPC5 */
CPU_ID_TPC_QMAN_ARC6 = 12, /* DCORE1_TPC0 */
CPU_ID_TPC_QMAN_ARC7 = 13, /* DCORE1_TPC1 */
CPU_ID_TPC_QMAN_ARC8 = 14, /* DCORE1_TPC2 */
CPU_ID_TPC_QMAN_ARC9 = 15, /* DCORE1_TPC3 */
CPU_ID_TPC_QMAN_ARC10 = 16, /* DCORE1_TPC4 */
CPU_ID_TPC_QMAN_ARC11 = 17, /* DCORE1_TPC5 */
CPU_ID_TPC_QMAN_ARC12 = 18, /* DCORE2_TPC0 */
CPU_ID_TPC_QMAN_ARC13 = 19, /* DCORE2_TPC1 */
CPU_ID_TPC_QMAN_ARC14 = 20, /* DCORE2_TPC2 */
CPU_ID_TPC_QMAN_ARC15 = 21, /* DCORE2_TPC3 */
CPU_ID_TPC_QMAN_ARC16 = 22, /* DCORE2_TPC4 */
CPU_ID_TPC_QMAN_ARC17 = 23, /* DCORE2_TPC5 */
CPU_ID_TPC_QMAN_ARC18 = 24, /* DCORE3_TPC0 */
CPU_ID_TPC_QMAN_ARC19 = 25, /* DCORE3_TPC1 */
CPU_ID_TPC_QMAN_ARC20 = 26, /* DCORE3_TPC2 */
CPU_ID_TPC_QMAN_ARC21 = 27, /* DCORE3_TPC3 */
CPU_ID_TPC_QMAN_ARC22 = 28, /* DCORE3_TPC4 */
CPU_ID_TPC_QMAN_ARC23 = 29, /* DCORE3_TPC5 */
CPU_ID_TPC_QMAN_ARC24 = 30, /* DCORE0_TPC6 - Never present */
#define CPU_ID_MME_QMAN_ARC0 31 /* DCORE0_MME0 */
#define CPU_ID_MME_QMAN_ARC1 32 /* DCORE2_MME0 */
CPU_ID_MME_QMAN_ARC0 = 31, /* DCORE0_MME0 */
CPU_ID_MME_QMAN_ARC1 = 32, /* DCORE2_MME0 */
#define CPU_ID_EDMA_QMAN_ARC0 33 /* DCORE0_EDMA0 */
#define CPU_ID_EDMA_QMAN_ARC1 34 /* DCORE0_EDMA1 */
#define CPU_ID_EDMA_QMAN_ARC2 35 /* DCORE1_EDMA0 */
#define CPU_ID_EDMA_QMAN_ARC3 36 /* DCORE1_EDMA1 */
#define CPU_ID_EDMA_QMAN_ARC4 37 /* DCORE2_EDMA0 */
#define CPU_ID_EDMA_QMAN_ARC5 38 /* DCORE2_EDMA1 */
#define CPU_ID_EDMA_QMAN_ARC6 39 /* DCORE3_EDMA0 */
#define CPU_ID_EDMA_QMAN_ARC7 40 /* DCORE3_EDMA1 */
CPU_ID_EDMA_QMAN_ARC0 = 33, /* DCORE0_EDMA0 */
CPU_ID_EDMA_QMAN_ARC1 = 34, /* DCORE0_EDMA1 */
CPU_ID_EDMA_QMAN_ARC2 = 35, /* DCORE1_EDMA0 */
CPU_ID_EDMA_QMAN_ARC3 = 36, /* DCORE1_EDMA1 */
CPU_ID_EDMA_QMAN_ARC4 = 37, /* DCORE2_EDMA0 */
CPU_ID_EDMA_QMAN_ARC5 = 38, /* DCORE2_EDMA1 */
CPU_ID_EDMA_QMAN_ARC6 = 39, /* DCORE3_EDMA0 */
CPU_ID_EDMA_QMAN_ARC7 = 40, /* DCORE3_EDMA1 */
#define CPU_ID_PDMA_QMAN_ARC0 41 /* DCORE0_PDMA0 */
#define CPU_ID_PDMA_QMAN_ARC1 42 /* DCORE0_PDMA1 */
CPU_ID_PDMA_QMAN_ARC0 = 41, /* DCORE0_PDMA0 */
CPU_ID_PDMA_QMAN_ARC1 = 42, /* DCORE0_PDMA1 */
#define CPU_ID_ROT_QMAN_ARC0 43 /* ROT0 */
#define CPU_ID_ROT_QMAN_ARC1 44 /* ROT1 */
CPU_ID_ROT_QMAN_ARC0 = 43, /* ROT0 */
CPU_ID_ROT_QMAN_ARC1 = 44, /* ROT1 */
#define CPU_ID_NIC_QMAN_ARC0 45 /* NIC0_0 */
#define CPU_ID_NIC_QMAN_ARC1 46 /* NIC0_1 */
#define CPU_ID_NIC_QMAN_ARC2 47 /* NIC1_0 */
#define CPU_ID_NIC_QMAN_ARC3 48 /* NIC1_1 */
#define CPU_ID_NIC_QMAN_ARC4 49 /* NIC2_0 */
#define CPU_ID_NIC_QMAN_ARC5 50 /* NIC2_1 */
#define CPU_ID_NIC_QMAN_ARC6 51 /* NIC3_0 */
#define CPU_ID_NIC_QMAN_ARC7 52 /* NIC3_1 */
#define CPU_ID_NIC_QMAN_ARC8 53 /* NIC4_0 */
#define CPU_ID_NIC_QMAN_ARC9 54 /* NIC4_1 */
#define CPU_ID_NIC_QMAN_ARC10 55 /* NIC5_0 */
#define CPU_ID_NIC_QMAN_ARC11 56 /* NIC5_1 */
#define CPU_ID_NIC_QMAN_ARC12 57 /* NIC6_0 */
#define CPU_ID_NIC_QMAN_ARC13 58 /* NIC6_1 */
#define CPU_ID_NIC_QMAN_ARC14 59 /* NIC7_0 */
#define CPU_ID_NIC_QMAN_ARC15 60 /* NIC7_1 */
#define CPU_ID_NIC_QMAN_ARC16 61 /* NIC8_0 */
#define CPU_ID_NIC_QMAN_ARC17 62 /* NIC8_1 */
#define CPU_ID_NIC_QMAN_ARC18 63 /* NIC9_0 */
#define CPU_ID_NIC_QMAN_ARC19 64 /* NIC9_1 */
#define CPU_ID_NIC_QMAN_ARC20 65 /* NIC10_0 */
#define CPU_ID_NIC_QMAN_ARC21 66 /* NIC10_1 */
#define CPU_ID_NIC_QMAN_ARC22 67 /* NIC11_0 */
#define CPU_ID_NIC_QMAN_ARC23 68 /* NIC11_1 */
CPU_ID_NIC_QMAN_ARC0 = 45, /* NIC0_0 */
CPU_ID_NIC_QMAN_ARC1 = 46, /* NIC0_1 */
CPU_ID_NIC_QMAN_ARC2 = 47, /* NIC1_0 */
CPU_ID_NIC_QMAN_ARC3 = 48, /* NIC1_1 */
CPU_ID_NIC_QMAN_ARC4 = 49, /* NIC2_0 */
CPU_ID_NIC_QMAN_ARC5 = 50, /* NIC2_1 */
CPU_ID_NIC_QMAN_ARC6 = 51, /* NIC3_0 */
CPU_ID_NIC_QMAN_ARC7 = 52, /* NIC3_1 */
CPU_ID_NIC_QMAN_ARC8 = 53, /* NIC4_0 */
CPU_ID_NIC_QMAN_ARC9 = 54, /* NIC4_1 */
CPU_ID_NIC_QMAN_ARC10 = 55, /* NIC5_0 */
CPU_ID_NIC_QMAN_ARC11 = 56, /* NIC5_1 */
CPU_ID_NIC_QMAN_ARC12 = 57, /* NIC6_0 */
CPU_ID_NIC_QMAN_ARC13 = 58, /* NIC6_1 */
CPU_ID_NIC_QMAN_ARC14 = 59, /* NIC7_0 */
CPU_ID_NIC_QMAN_ARC15 = 60, /* NIC7_1 */
CPU_ID_NIC_QMAN_ARC16 = 61, /* NIC8_0 */
CPU_ID_NIC_QMAN_ARC17 = 62, /* NIC8_1 */
CPU_ID_NIC_QMAN_ARC18 = 63, /* NIC9_0 */
CPU_ID_NIC_QMAN_ARC19 = 64, /* NIC9_1 */
CPU_ID_NIC_QMAN_ARC20 = 65, /* NIC10_0 */
CPU_ID_NIC_QMAN_ARC21 = 66, /* NIC10_1 */
CPU_ID_NIC_QMAN_ARC22 = 67, /* NIC11_0 */
CPU_ID_NIC_QMAN_ARC23 = 68, /* NIC11_1 */
#define CPU_ID_MAX 69
#define CPU_ID_SCHED_MAX 6
CPU_ID_MAX = 69,
CPU_ID_SCHED_MAX = 6,
#define CPU_ID_ALL 0xFE
#define CPU_ID_INVALID 0xFF
CPU_ID_ALL = 0xFE,
CPU_ID_INVALID = 0xFF,
};
enum arc_regions_t {
ARC_REGION0_UNSED = 0,
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h
View file @ 2fd7db3c
......@@ -150,8 +150,7 @@
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK \
0x100000
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK 0x100000
/* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */
#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0
......@@ -235,23 +234,19 @@
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK \
0xFFFFFFFF
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK \
0xFFFFFFFF
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK \
0xFFFFFFFF
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK \
0xFFFFFFFF
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */
#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h
View file @ 2fd7db3c
......@@ -92,8 +92,7 @@
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK \
0x7E00000
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000
/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */
#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0
......@@ -228,12 +227,8 @@
#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7
/* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */
#define \
DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT \
0
#define \
DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \
0x1
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2
......@@ -261,53 +256,43 @@ DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK \
0x1FF
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h
View file @ 2fd7db3c
......@@ -20,8 +20,7 @@
*****************************************
*/
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 \
0x40CB280
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 0x40CB280
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW 0x40CB284
......@@ -29,8 +28,7 @@
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP 0x40CB28C
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 \
0x40CB290
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 0x40CB290
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT 0x40CB294
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h
View file @ 2fd7db3c
......@@ -78,8 +78,7 @@
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK \
0x10000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK 0x10000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18
......@@ -87,11 +86,9 @@
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK \
0x100000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK 0x100000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK \
0x200000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK 0x200000
/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h
View file @ 2fd7db3c
......@@ -106,8 +106,7 @@
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK \
0x8
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5
......@@ -117,8 +116,7 @@
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \
0x100
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
View file @ 2fd7db3c
......@@ -48,8 +48,7 @@
#define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034
#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG \
0x4C0203C
#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG 0x4C0203C
#define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h
View file @ 2fd7db3c
......@@ -116,8 +116,7 @@
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \
0x100
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h
View file @ 2fd7db3c
......@@ -228,8 +228,7 @@
/* PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION */
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \
0x1
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2
......
drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h
View file @ 2fd7db3c
......@@ -1306,11 +1306,9 @@
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_SHIFT 12
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_MASK 0x3F000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_SHIFT 18
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK \
0xFC0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK 0xFC0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_SHIFT 24
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK \
0x3F000000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK 0x3F000000
/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_SHIFT 0
......@@ -1322,24 +1320,17 @@
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_SHIFT 13
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_MASK 0x2000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_SHIFT 14
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK \
0x4000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT \
16
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK \
0xFF0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK 0x4000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT 16
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK 0xFF0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_SHIFT 24
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_MASK 0x7000000
/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT \
0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK \
0xFFFF
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT \
16
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK \
0xFFFF0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK 0xFFFF
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT 16
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK 0xFFFF0000
/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_SHIFT 0
......
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