Skip to content

L
linux
Commit 30d430d9 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files
Options

Merge tag 'uniphier-dt-v4.9' of... 

Merge tag 'uniphier-dt-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt

Merge "UniPhier ARM SoC DT updates for v4.9" from Masahiro Yamada:

* Match DT names other projects and documents
* Switch over to PSCI
* Use clock/reset drivers
* Misc

* tag 'uniphier-dt-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  ARM: dts: uniphier: add specific compatible to SoC-Glue node
  ARM: dts: uniphier: use clock/reset controllers
  ARM: dts: uniphier: switch over to PSCI
  ARM: dts: uniphier: match DT names to other projects and documents
  ARM: dts: uniphier: remove a whitespace after tabs
parents 6f7f9e44 cb165937
Hide whitespace changes
Inline Side-by-side
Showing with 376 additions and 198 deletions
arch/arm/boot/dts/Makefile
View file @ 30d430d9
......@@ -836,15 +836,15 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-ccu8540.dtb \
ste-ccu9540.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ace.dtb \
uniphier-ph1-pro4-ref.dtb \
uniphier-ph1-pro4-sanji.dtb \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-sld8-ref.dtb \
uniphier-proxstream2-gentil.dtb \
uniphier-proxstream2-vodka.dtb
uniphier-ld4-ref.dtb \
uniphier-ld6b-ref.dtb \
uniphier-pro4-ace.dtb \
uniphier-pro4-ref.dtb \
uniphier-pro4-sanji.dtb \
uniphier-pxs2-gentil.dtb \
uniphier-pxs2-vodka.dtb \
uniphier-sld3-ref.dtb \
uniphier-sld8-ref.dtb
dtb-$(CONFIG_ARCH_VERSATILE) += \
versatile-ab.dtb \
versatile-pb.dtb
......
arch/arm/boot/dts/uniphier-common32.dtsi
View file @ 30d430d9
/*
* Device Tree Source commonly used by UniPhier ARM SoCs
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -45,6 +46,11 @@
/include/ "skeleton.dtsi"
/ {
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
refclk: ref {
#clock-cells = <0>;
......@@ -66,7 +72,7 @@ serial0: serial@54006800 {
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart_clk>;
clocks = <&peri_clk 0>;
};
serial1: serial@54006900 {
......@@ -76,7 +82,7 @@ serial1: serial@54006900 {
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart_clk>;
clocks = <&peri_clk 1>;
};
serial2: serial@54006a00 {
......@@ -86,7 +92,7 @@ serial2: serial@54006a00 {
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&uart_clk>;
clocks = <&peri_clk 2>;
};
serial3: serial@54006b00 {
......@@ -96,7 +102,7 @@ serial3: serial@54006b00 {
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&uart_clk>;
clocks = <&peri_clk 3>;
};
system_bus: system-bus@58c00000 {
......@@ -114,6 +120,34 @@ smpctrl@59800000 {
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
mio_clk: clock {
#clock-cells = <1>;
};
mio_rst: reset {
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
#clock-cells = <1>;
};
peri_rst: reset {
#reset-cells = <1>;
};
};
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
......@@ -137,11 +171,26 @@ intc: interrupt-controller@60001000 {
};
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
compatible = "socionext,uniphier-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
pinctrl: pinctrl {
/* specify compatible in each SoC DTSI */
/* specify compatible in each SoC DTSI */
};
};
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
sys_clk: clock {
#clock-cells = <1>;
};
sys_rst: reset {
#reset-cells = <1>;
};
};
};
......
arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts → arch/arm/boot/dts/uniphier-ld4-ref.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-LD4 Reference Board
* Device Tree Source for UniPhier LD4 Reference Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,13 +44,13 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-ld4.dtsi"
/include/ "uniphier-ld4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-LD4 Reference Board";
compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4";
model = "UniPhier LD4 Reference Board";
compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-ph1-ld4.dtsi → arch/arm/boot/dts/uniphier-ld4.dtsi
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-LD4 SoC
* Device Tree Source for UniPhier LD4 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -45,7 +46,7 @@
/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-ld4";
compatible = "socionext,uniphier-ld4";
cpus {
#address-cells = <1>;
......@@ -55,6 +56,7 @@ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
......@@ -65,18 +67,6 @@ arm_timer_clk: arm_timer_clk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <36864000>;
};
iobus_clk: iobus_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
};
};
......@@ -101,7 +91,7 @@ i2c0: i2c@58400000 {
interrupts = <0 41 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
......@@ -114,7 +104,7 @@ i2c1: i2c@58480000 {
interrupts = <0 42 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
......@@ -127,7 +117,7 @@ i2c2: i2c@58500000 {
interrupts = <0 43 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
......@@ -140,7 +130,7 @@ i2c3: i2c@58580000 {
interrupts = <0 44 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
......@@ -151,6 +141,8 @@ usb0: usb@5a800100 {
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
};
usb1: usb@5a810100 {
......@@ -160,6 +152,8 @@ usb1: usb@5a810100 {
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
};
usb2: usb@5a820100 {
......@@ -169,6 +163,8 @@ usb2: usb@5a820100 {
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
};
};
......@@ -181,6 +177,31 @@ &serial3 {
interrupts = <0 29 4>;
};
&mio_clk {
compatible = "socionext,uniphier-ld4-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-ld4-mio-reset";
resets = <&sys_rst 7>;
};
&peri_clk {
compatible = "socionext,uniphier-ld4-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-ld4-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-ld4-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-ld4-clock";
};
&sys_rst {
compatible = "socionext,uniphier-ld4-reset";
};
arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts → arch/arm/boot/dts/uniphier-ld6b-ref.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-LD6b Reference Board
* Device Tree Source for UniPhier LD6b Reference Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,13 +44,13 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-ld6b.dtsi"
/include/ "uniphier-ld6b.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-LD6b Reference Board";
compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b";
model = "UniPhier LD6b Reference Board";
compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi → arch/arm/boot/dts/uniphier-ld6b.dtsi
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-LD6b SoC
* Device Tree Source for UniPhier LD6b SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,14 +44,14 @@
*/
/*
* PH1-LD6b consists of two silicon dies: D-chip and A-chip.
* The D-chip (digital chip) is the same as the ProXstream2 die.
* Reuse the ProXstream2 device tree with some properties overridden.
* LD6b consists of two silicon dies: D-chip and A-chip.
* The D-chip (digital chip) is the same as the PXs2 die.
* Reuse the PXs2 device tree with some properties overridden.
*/
/include/ "uniphier-proxstream2.dtsi"
/include/ "uniphier-pxs2.dtsi"
/ {
compatible = "socionext,ph1-ld6b";
compatible = "socionext,uniphier-ld6b";
};
/* UART3 unavailable: the pads are not wired to the package balls */
......@@ -59,7 +60,7 @@ &serial3 {
};
/*
* PH1-LD6b and ProXstream2 have completely different packages,
* LD6b and PXs2 have completely different packages,
* which makes the pinctrl driver unshareable.
*/
&pinctrl {
......
arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts → arch/arm/boot/dts/uniphier-pro4-ace.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-Pro4 Ace Board
* Device Tree Source for UniPhier Pro4 Ace Board
*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,11 +44,11 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-pro4.dtsi"
/include/ "uniphier-pro4.dtsi"
/ {
model = "UniPhier PH1-Pro4 Ace Board";
compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4";
model = "UniPhier Pro4 Ace Board";
compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts → arch/arm/boot/dts/uniphier-pro4-ref.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-Pro4 Reference Board
* Device Tree Source for UniPhier Pro4 Reference Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,13 +44,13 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-pro4.dtsi"
/include/ "uniphier-pro4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-Pro4 Reference Board";
compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4";
model = "UniPhier Pro4 Reference Board";
compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts → arch/arm/boot/dts/uniphier-pro4-sanji.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-Pro4 Sanji Board
* Device Tree Source for UniPhier Pro4 Sanji Board
*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,11 +44,11 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-pro4.dtsi"
/include/ "uniphier-pro4.dtsi"
/ {
model = "UniPhier PH1-Pro4 Sanji Board";
compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4";
model = "UniPhier Pro4 Sanji Board";
compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-ph1-pro4.dtsi → arch/arm/boot/dts/uniphier-pro4.dtsi
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-Pro4 SoC
* Device Tree Source for UniPhier Pro4 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -45,17 +46,17 @@
/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-pro4";
compatible = "socionext,uniphier-pro4";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
......@@ -63,6 +64,7 @@ cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
......@@ -73,18 +75,6 @@ arm_timer_clk: arm_timer_clk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <73728000>;
};
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
};
......@@ -109,7 +99,7 @@ i2c0: i2c@58780000 {
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
......@@ -122,7 +112,7 @@ i2c1: i2c@58781000 {
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
......@@ -135,7 +125,7 @@ i2c2: i2c@58782000 {
interrupts = <0 43 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <100000>;
};
......@@ -148,7 +138,7 @@ i2c3: i2c@58783000 {
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
......@@ -161,7 +151,7 @@ i2c5: i2c@58785000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
......@@ -172,7 +162,7 @@ i2c6: i2c@58786000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 10>;
clock-frequency = <400000>;
};
......@@ -183,6 +173,8 @@ usb2: usb@5a800100 {
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
};
usb3: usb@5a810100 {
......@@ -192,6 +184,8 @@ usb3: usb@5a810100 {
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
};
};
......@@ -199,6 +193,31 @@ &refclk {
clock-frequency = <25000000>;
};
&mio_clk {
compatible = "socionext,uniphier-pro4-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pro4-mio-reset";
resets = <&sys_rst 7>;
};
&peri_clk {
compatible = "socionext,uniphier-pro4-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-pro4-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-pro4-clock";
};
&sys_rst {
compatible = "socionext,uniphier-pro4-reset";
};
arch/arm/boot/dts/uniphier-ph1-pro5.dtsi → arch/arm/boot/dts/uniphier-pro5.dtsi
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-Pro5 SoC
* Device Tree Source for UniPhier Pro5 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -45,17 +46,17 @@
/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-pro5";
compatible = "socionext,uniphier-pro5";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
......@@ -63,6 +64,7 @@ cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
......@@ -73,18 +75,6 @@ arm_timer_clk: arm_timer_clk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <73728000>;
};
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
};
......@@ -121,7 +111,7 @@ i2c0: i2c@58780000 {
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
......@@ -134,7 +124,7 @@ i2c1: i2c@58781000 {
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
......@@ -147,7 +137,7 @@ i2c2: i2c@58782000 {
interrupts = <0 43 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <100000>;
};
......@@ -160,7 +150,7 @@ i2c3: i2c@58783000 {
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
......@@ -173,7 +163,7 @@ i2c5: i2c@58785000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
......@@ -184,7 +174,7 @@ i2c6: i2c@58786000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 10>;
clock-frequency = <400000>;
};
};
......@@ -193,6 +183,30 @@ &refclk {
clock-frequency = <20000000>;
};
&mio_clk {
compatible = "socionext,uniphier-pro5-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pro5-mio-reset";
};
&peri_clk {
compatible = "socionext,uniphier-pro5-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-pro5-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-pro5-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-pro5-clock";
};
&sys_rst {
compatible = "socionext,uniphier-pro5-reset";
};
arch/arm/boot/dts/uniphier-proxstream2-gentil.dts → arch/arm/boot/dts/uniphier-pxs2-gentil.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier ProXstream2 Gentil Board
* Device Tree Source for UniPhier PXs2 Gentil Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,11 +44,12 @@
*/
/dts-v1/;
/include/ "uniphier-proxstream2.dtsi"
/include/ "uniphier-pxs2.dtsi"
/ {
model = "UniPhier ProXstream2 Gentil Board";
compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
model = "UniPhier PXs2 Gentil Board";
compatible = "socionext,uniphier-pxs2-gentil",
"socionext,uniphier-pxs2";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-proxstream2-vodka.dts → arch/arm/boot/dts/uniphier-pxs2-vodka.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier ProXstream2 Vodka Board
* Device Tree Source for UniPhier PXs2 Vodka Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,11 +44,11 @@
*/
/dts-v1/;
/include/ "uniphier-proxstream2.dtsi"
/include/ "uniphier-pxs2.dtsi"
/ {
model = "UniPhier ProXstream2 Vodka Board";
compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
model = "UniPhier PXs2 Vodka Board";
compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-proxstream2.dtsi → arch/arm/boot/dts/uniphier-pxs2.dtsi
View file @ 30d430d9
/*
* Device Tree Source for UniPhier ProXstream2 SoC
* Device Tree Source for UniPhier PXs2 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -45,17 +46,17 @@
/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,proxstream2";
compatible = "socionext,uniphier-pxs2";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
......@@ -63,6 +64,7 @@ cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
......@@ -70,6 +72,7 @@ cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
enable-method = "psci";
next-level-cache = <&l2>;
};
......@@ -77,6 +80,7 @@ cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
......@@ -87,18 +91,6 @@ arm_timer_clk: arm_timer_clk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <88900000>;
};
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
};
......@@ -123,7 +115,7 @@ i2c0: i2c@58780000 {
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
......@@ -136,7 +128,7 @@ i2c1: i2c@58781000 {
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
......@@ -149,7 +141,7 @@ i2c2: i2c@58782000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
interrupts = <0 43 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <100000>;
};
......@@ -162,7 +154,7 @@ i2c3: i2c@58783000 {
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
......@@ -173,7 +165,7 @@ i2c4: i2c@58784000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 8>;
clock-frequency = <400000>;
};
......@@ -184,7 +176,7 @@ i2c5: i2c@58785000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
......@@ -195,7 +187,7 @@ i2c6: i2c@58786000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 10>;
clock-frequency = <400000>;
};
};
......@@ -204,6 +196,30 @@ &refclk {
clock-frequency = <25000000>;
};
&mio_clk {
compatible = "socionext,uniphier-pxs2-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pxs2-mio-reset";
};
&peri_clk {
compatible = "socionext,uniphier-pxs2-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-pxs2-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-pxs2-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-pxs2-clock";
};
&sys_rst {
compatible = "socionext,uniphier-pxs2-reset";
};
arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts → arch/arm/boot/dts/uniphier-sld3-ref.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-sLD3 Reference Board
* Device Tree Source for UniPhier sLD3 Reference Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,13 +44,13 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-sld3.dtsi"
/include/ "uniphier-sld3.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-sLD3 Reference Board";
compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3";
model = "UniPhier sLD3 Reference Board";
compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-ph1-sld3.dtsi → arch/arm/boot/dts/uniphier-sld3.dtsi
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-sLD3 SoC
* Device Tree Source for UniPhier sLD3 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -45,17 +46,17 @@
/include/ "skeleton.dtsi"
/ {
compatible = "socionext,ph1-sld3";
compatible = "socionext,uniphier-sld3";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
......@@ -63,10 +64,16 @@ cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
refclk: ref {
#clock-cells = <0>;
......@@ -79,18 +86,6 @@ arm_timer_clk: arm_timer_clk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <36864000>;
};
iobus_clk: iobus_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
};
soc {
......@@ -139,7 +134,7 @@ serial0: serial@54006800 {
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
clocks = <&uart_clk>;
clocks = <&sys_clk 0>;
fifo-size = <64>;
};
......@@ -148,7 +143,7 @@ serial1: serial@54006900 {
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
clocks = <&uart_clk>;
clocks = <&sys_clk 0>;
fifo-size = <64>;
};
......@@ -157,7 +152,7 @@ serial2: serial@54006a00 {
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
clocks = <&uart_clk>;
clocks = <&sys_clk 0>;
fifo-size = <64>;
};
......@@ -168,7 +163,7 @@ i2c0: i2c@58400000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -179,7 +174,7 @@ i2c1: i2c@58480000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -190,7 +185,7 @@ i2c2: i2c@58500000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -201,7 +196,7 @@ i2c3: i2c@58580000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -212,7 +207,7 @@ i2c4: i2c@58600000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <400000>;
};
......@@ -229,6 +224,22 @@ smpctrl@59800000 {
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-sld3-mio-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-sld3-mio-reset";
#reset-cells = <1>;
};
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
......@@ -256,5 +267,21 @@ usb3: usb@5a830100 {
reg = <0x5a830100 0x100>;
interrupts = <0 83 4>;
};
sysctrl@f1840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
reg = <0xf1840000 0x4000>;
sys_clk: clock {
compatible = "socionext,uniphier-sld3-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-sld3-reset";
#reset-cells = <1>;
};
};
};
};
arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts → arch/arm/boot/dts/uniphier-sld8-ref.dts
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-sLD8 Reference Board
* Device Tree Source for UniPhier sLD8 Reference Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -43,13 +44,13 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-sld8.dtsi"
/include/ "uniphier-sld8.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-sLD8 Reference Board";
compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8";
model = "UniPhier sLD8 Reference Board";
compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
memory {
device_type = "memory";
......
arch/arm/boot/dts/uniphier-ph1-sld8.dtsi → arch/arm/boot/dts/uniphier-sld8.dtsi
View file @ 30d430d9
/*
* Device Tree Source for UniPhier PH1-sLD8 SoC
* Device Tree Source for UniPhier sLD8 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
......@@ -45,7 +46,7 @@
/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-sld8";
compatible = "socionext,uniphier-sld8";
cpus {
#address-cells = <1>;
......@@ -55,6 +56,7 @@ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
......@@ -65,18 +67,6 @@ arm_timer_clk: arm_timer_clk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
iobus_clk: iobus_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
};
};
......@@ -101,7 +91,7 @@ i2c0: i2c@58400000 {
interrupts = <0 41 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
......@@ -114,7 +104,7 @@ i2c1: i2c@58480000 {
interrupts = <0 42 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
......@@ -127,7 +117,7 @@ i2c2: i2c@58500000 {
interrupts = <0 43 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
......@@ -140,7 +130,7 @@ i2c3: i2c@58580000 {
interrupts = <0 44 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&iobus_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
......@@ -151,6 +141,8 @@ usb0: usb@5a800100 {
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
};
usb1: usb@5a810100 {
......@@ -160,6 +152,8 @@ usb1: usb@5a810100 {
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
};
usb2: usb@5a820100 {
......@@ -169,6 +163,8 @@ usb2: usb@5a820100 {
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
};
};
......@@ -180,6 +176,31 @@ &serial3 {
interrupts = <0 29 4>;
};
&mio_clk {
compatible = "socionext,uniphier-sld8-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-sld8-mio-reset";
resets = <&sys_rst 7>;
};
&peri_clk {
compatible = "socionext,uniphier-sld8-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-sld8-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-sld8-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-sld8-clock";
};
&sys_rst {
compatible = "socionext,uniphier-sld8-reset";
};
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7