Commit 30e58102 authored by yipechai's avatar yipechai Committed by Alex Deucher

drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in mca ras block

Remove redundant calls of amdgpu_ras_block_late_fini in mca ras block.
Signed-off-by: default avataryipechai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 149d7ba1
...@@ -70,9 +70,3 @@ void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, ...@@ -70,9 +70,3 @@ void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
amdgpu_mca_reset_error_count(adev, mc_status_addr); amdgpu_mca_reset_error_count(adev, mc_status_addr);
} }
void amdgpu_mca_ras_fini(struct amdgpu_device *adev,
struct amdgpu_mca_ras *mca_dev)
{
amdgpu_ras_block_late_fini(adev, mca_dev->ras_if);
}
\ No newline at end of file
...@@ -56,7 +56,4 @@ void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, ...@@ -56,7 +56,4 @@ void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
uint64_t mc_status_addr, uint64_t mc_status_addr,
void *ras_error_status); void *ras_error_status);
void amdgpu_mca_ras_fini(struct amdgpu_device *adev,
struct amdgpu_mca_ras *mca_dev);
#endif #endif
...@@ -37,11 +37,6 @@ static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, ...@@ -37,11 +37,6 @@ static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
ras_error_status); ras_error_status);
} }
static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
amdgpu_mca_ras_fini(adev, &adev->mca.mp0);
}
static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj, static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
enum amdgpu_ras_block block, uint32_t sub_block_index) enum amdgpu_ras_block block, uint32_t sub_block_index)
{ {
...@@ -71,7 +66,7 @@ struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = { ...@@ -71,7 +66,7 @@ struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
}, },
.hw_ops = &mca_v3_0_mp0_hw_ops, .hw_ops = &mca_v3_0_mp0_hw_ops,
.ras_block_match = mca_v3_0_ras_block_match, .ras_block_match = mca_v3_0_ras_block_match,
.ras_fini = mca_v3_0_mp0_ras_fini, .ras_fini = amdgpu_ras_block_late_fini,
}, },
}; };
...@@ -83,11 +78,6 @@ static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, ...@@ -83,11 +78,6 @@ static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
ras_error_status); ras_error_status);
} }
static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
amdgpu_mca_ras_fini(adev, &adev->mca.mp1);
}
const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = { const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
.query_ras_error_count = mca_v3_0_mp1_query_ras_error_count, .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
.query_ras_error_address = NULL, .query_ras_error_address = NULL,
...@@ -103,7 +93,7 @@ struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = { ...@@ -103,7 +93,7 @@ struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
}, },
.hw_ops = &mca_v3_0_mp1_hw_ops, .hw_ops = &mca_v3_0_mp1_hw_ops,
.ras_block_match = mca_v3_0_ras_block_match, .ras_block_match = mca_v3_0_ras_block_match,
.ras_fini = mca_v3_0_mp1_ras_fini, .ras_fini = amdgpu_ras_block_late_fini,
}, },
}; };
...@@ -115,11 +105,6 @@ static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, ...@@ -115,11 +105,6 @@ static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
ras_error_status); ras_error_status);
} }
static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
amdgpu_mca_ras_fini(adev, &adev->mca.mpio);
}
const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = { const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
.query_ras_error_count = mca_v3_0_mpio_query_ras_error_count, .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
.query_ras_error_address = NULL, .query_ras_error_address = NULL,
...@@ -135,7 +120,7 @@ struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = { ...@@ -135,7 +120,7 @@ struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
}, },
.hw_ops = &mca_v3_0_mpio_hw_ops, .hw_ops = &mca_v3_0_mpio_hw_ops,
.ras_block_match = mca_v3_0_ras_block_match, .ras_block_match = mca_v3_0_ras_block_match,
.ras_fini = mca_v3_0_mpio_ras_fini, .ras_fini = amdgpu_ras_block_late_fini,
}, },
}; };
......
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