Commit 31564b8b authored by Kefeng Wang's avatar Kefeng Wang Committed by Palmer Dabbelt

riscv: Add HAVE_IRQ_TIME_ACCOUNTING

RISCV_TIMER/CLINT_TIMER is required for RISC-V system, and it
provides sched_clock, which allow us to enable IRQ_TIME_ACCOUNTING.
Signed-off-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent da815582
......@@ -23,7 +23,7 @@
| openrisc: | TODO |
| parisc: | .. |
| powerpc: | ok |
| riscv: | TODO |
| riscv: | ok |
| s390: | .. |
| sh: | TODO |
| sparc: | .. |
......
......@@ -68,6 +68,7 @@ config RISCV
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
select HAVE_GENERIC_VDSO if MMU && 64BIT
select HAVE_IRQ_TIME_ACCOUNTING
select HAVE_PCI
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
......
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