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Commit 3179798d authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'sti-dt-for-v4.9-3' of... 

Merge tag 'sti-dt-for-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/dt

Pull "STi clock improvement for video playback" from Patrice Chotard:

This serie allows to increase video resolutions and make audio
adjustment during a video playback for STiH407 family socs.

* tag 'sti-dt-for-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
  ARM: dts: STiH410: clock configuration to address 720p and 1080p
  ARM: dts: STi: STiH407: clock configuration to address 720p and 1080p
  ARM: dts: STiH418: Enable synchronous clock mode for video clocks
  ARM: dts: STiH410: Enable synchronous clock mode for video clocks
  ARM: dts: STiH407: Enable synchronous clock mode for video clocks
  ARM: dts: STiH418: Enable clock propagation for audio clocks
  ARM: dts: STiH410: Enable clock propagation for audio clocks
  ARM: dts: STiH407: Enable clock propagation for audio clocks
  ARM: dts: STiH4xx: Simplify clock binding of STiH4xx platforms
parents a60bb261 3a74152c
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Showing with 57 additions and 37 deletions
arch/arm/boot/dts/stih407-clock.dtsi
View file @ 3179798d
...@@ -42,7 +42,7 @@ clockgen-a9@92b0000 { ...@@ -42,7 +42,7 @@ clockgen-a9@92b0000 {
clockgen_a9_pll: clockgen-a9-pll { clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -55,7 +55,7 @@ clockgen_a9_pll: clockgen-a9-pll { ...@@ -55,7 +55,7 @@ clockgen_a9_pll: clockgen-a9-pll {
*/ */
clk_m_a9: clk-m-a9@92b0000 { clk_m_a9: clk-m-a9@92b0000 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; compatible = "st,stih407-clkgen-a9-mux";
reg = <0x92b0000 0x10000>; reg = <0x92b0000 0x10000>;
clocks = <&clockgen_a9_pll 0>, clocks = <&clockgen_a9_pll 0>,
...@@ -96,7 +96,7 @@ clockgen-a@090ff000 { ...@@ -96,7 +96,7 @@ clockgen-a@090ff000 {
clk_s_a0_pll: clk-s-a0-pll { clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -117,7 +117,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { ...@@ -117,7 +117,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs"; compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>; reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -134,7 +134,7 @@ clk_s_c0: clockgen-c@09103000 { ...@@ -134,7 +134,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 { clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -143,7 +143,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { ...@@ -143,7 +143,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 { clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll1";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -199,7 +199,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen { ...@@ -199,7 +199,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9104000 0x1000>; reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -216,7 +216,7 @@ clockgen-d0@09104000 { ...@@ -216,7 +216,7 @@ clockgen-d0@09104000 {
clk_s_d0_flexgen: clk-s-d0-flexgen { clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,flexgen"; compatible = "st,flexgen-audio", "st,flexgen";
clocks = <&clk_s_d0_quadfs 0>, clocks = <&clk_s_d0_quadfs 0>,
<&clk_s_d0_quadfs 1>, <&clk_s_d0_quadfs 1>,
...@@ -233,7 +233,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { ...@@ -233,7 +233,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9106000 0x1000>; reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -256,7 +256,7 @@ clockgen-d2@x9106000 { ...@@ -256,7 +256,7 @@ clockgen-d2@x9106000 {
clk_s_d2_flexgen: clk-s-d2-flexgen { clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,flexgen"; compatible = "st,flexgen-video", "st,flexgen";
clocks = <&clk_s_d2_quadfs 0>, clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 1>,
...@@ -287,7 +287,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { ...@@ -287,7 +287,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9107000 0x1000>; reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
arch/arm/boot/dts/stih407.dtsi
View file @ 3179798d
...@@ -16,7 +16,10 @@ sti-display-subsystem { ...@@ -16,7 +16,10 @@ sti-display-subsystem {
#size-cells = <1>; #size-cells = <1>;
assigned-clocks = <&clk_s_d2_quadfs 0>, assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_c0_flexgen CLK_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
<&clk_s_d2_flexgen CLK_PIX_GDP1>, <&clk_s_d2_flexgen CLK_PIX_GDP1>,
...@@ -26,14 +29,21 @@ sti-display-subsystem { ...@@ -26,14 +29,21 @@ sti-display-subsystem {
assigned-clock-parents = <0>, assigned-clock-parents = <0>,
<0>, <0>,
<0>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_pll1 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>; <&clk_s_d2_quadfs 0>;
assigned-clock-rates = <297000000>, <297000000>; assigned-clock-rates = <297000000>,
<108000000>,
<0>,
<400000000>,
<400000000>;
ranges; ranges;
......
arch/arm/boot/dts/stih410-clock.dtsi
View file @ 3179798d
...@@ -44,7 +44,7 @@ clockgen-a9@92b0000 { ...@@ -44,7 +44,7 @@ clockgen-a9@92b0000 {
clockgen_a9_pll: clockgen-a9-pll { clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -98,7 +98,7 @@ clockgen-a@090ff000 { ...@@ -98,7 +98,7 @@ clockgen-a@090ff000 {
clk_s_a0_pll: clk-s-a0-pll { clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -122,7 +122,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { ...@@ -122,7 +122,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs"; compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>; reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -140,7 +140,7 @@ clk_s_c0: clockgen-c@09103000 { ...@@ -140,7 +140,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 { clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -150,7 +150,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { ...@@ -150,7 +150,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 { clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll1";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -218,7 +218,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen { ...@@ -218,7 +218,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9104000 0x1000>; reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -235,7 +235,7 @@ clockgen-d0@09104000 { ...@@ -235,7 +235,7 @@ clockgen-d0@09104000 {
clk_s_d0_flexgen: clk-s-d0-flexgen { clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,flexgen"; compatible = "st,flexgen-audio", "st,flexgen";
clocks = <&clk_s_d0_quadfs 0>, clocks = <&clk_s_d0_quadfs 0>,
<&clk_s_d0_quadfs 1>, <&clk_s_d0_quadfs 1>,
...@@ -254,7 +254,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { ...@@ -254,7 +254,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9106000 0x1000>; reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -277,7 +277,7 @@ clockgen-d2@x9106000 { ...@@ -277,7 +277,7 @@ clockgen-d2@x9106000 {
clk_s_d2_flexgen: clk-s-d2-flexgen { clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,flexgen"; compatible = "st,flexgen-video", "st,flexgen";
clocks = <&clk_s_d2_quadfs 0>, clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 1>,
...@@ -308,7 +308,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { ...@@ -308,7 +308,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9107000 0x1000>; reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
arch/arm/boot/dts/stih410.dtsi
View file @ 3179798d
...@@ -103,7 +103,10 @@ sti-display-subsystem { ...@@ -103,7 +103,10 @@ sti-display-subsystem {
#size-cells = <1>; #size-cells = <1>;
assigned-clocks = <&clk_s_d2_quadfs 0>, assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_c0_flexgen CLK_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
<&clk_s_d2_flexgen CLK_PIX_GDP1>, <&clk_s_d2_flexgen CLK_PIX_GDP1>,
...@@ -113,14 +116,21 @@ sti-display-subsystem { ...@@ -113,14 +116,21 @@ sti-display-subsystem {
assigned-clock-parents = <0>, assigned-clock-parents = <0>,
<0>, <0>,
<0>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_pll1 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>; <&clk_s_d2_quadfs 0>;
assigned-clock-rates = <297000000>, <297000000>; assigned-clock-rates = <297000000>,
<108000000>,
<0>,
<400000000>,
<400000000>;
ranges; ranges;
......
arch/arm/boot/dts/stih418-clock.dtsi
View file @ 3179798d
...@@ -44,7 +44,7 @@ clockgen-a9@92b0000 { ...@@ -44,7 +44,7 @@ clockgen-a9@92b0000 {
clockgen_a9_pll: clockgen-a9-pll { clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; compatible = "st,stih418-clkgen-plla9";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -98,7 +98,7 @@ clockgen-a@090ff000 { ...@@ -98,7 +98,7 @@ clockgen-a@090ff000 {
clk_s_a0_pll: clk-s-a0-pll { clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -120,7 +120,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { ...@@ -120,7 +120,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs"; compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>; reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 { ...@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 { clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { ...@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 { clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll1";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -212,7 +212,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen { ...@@ -212,7 +212,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9104000 0x1000>; reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -229,7 +229,7 @@ clockgen-d0@09104000 { ...@@ -229,7 +229,7 @@ clockgen-d0@09104000 {
clk_s_d0_flexgen: clk-s-d0-flexgen { clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,flexgen"; compatible = "st,flexgen-audio", "st,flexgen";
clocks = <&clk_s_d0_quadfs 0>, clocks = <&clk_s_d0_quadfs 0>,
<&clk_s_d0_quadfs 1>, <&clk_s_d0_quadfs 1>,
...@@ -248,7 +248,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { ...@@ -248,7 +248,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9106000 0x1000>; reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -271,7 +271,7 @@ clockgen-d2@x9106000 { ...@@ -271,7 +271,7 @@ clockgen-d2@x9106000 {
clk_s_d2_flexgen: clk-s-d2-flexgen { clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,flexgen"; compatible = "st,flexgen-video", "st,flexgen";
clocks = <&clk_s_d2_quadfs 0>, clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 1>,
...@@ -309,7 +309,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { ...@@ -309,7 +309,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs"; compatible = "st,quadfs";
reg = <0x9107000 0x1000>; reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
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