Commit 31f1ebe8 authored by Vojtech Pavlik's avatar Vojtech Pavlik

Merge suse.cz:/home/vojtech/bk/linus into suse.cz:/home/vojtech/bk/input

parents d84c369b 862e3994
......@@ -121,7 +121,6 @@ void die_if_kernel(char *str, struct pt_regs *regs)
!(((unsigned long) rw) & 0x7)) {
printk("Caller[%08lx]", rw->ins[7]);
print_symbol(": %s\n", rw->ins[7]);
printk("\n");
rw = (struct reg_window *)rw->ins[6];
}
}
......
......@@ -392,7 +392,7 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
if (pmd_present(*pmd) || !pmd_present(*pmd_k))
goto bad_area_nosemaphore;
pmd_val(*pmd) = pmd_val(*pmd_k);
*pmd = *pmd_k;
return;
}
}
......
......@@ -51,26 +51,6 @@
#include <asm/btfixup.h>
/*
* To support pagetables in highmem, Linux introduces APIs which
* return struct page* and generally manipulate page tables when
* they are not mapped into kernel space. Our hardware page tables
* are smaller than pages. We lump hardware tabes into big, page sized
* software tables.
*
* PMD_SHIFT determines the size of the area a second-level page table entry
* can map, and our pmd_t is 16 times larger than normal.
*/
#define SRMMU_PTRS_PER_PMD_SOFT 0x4 /* Each pmd_t contains 16 hard PTPs */
#define SRMMU_PTRS_PER_PTE_SOFT 0x400 /* 16 hard tables per 4K page */
#define SRMMU_PTE_SZ_SOFT 0x1000 /* same as above, in bytes */
#define SRMMU_PMD_SHIFT_SOFT 22
#define SRMMU_PMD_SIZE_SOFT (1UL << SRMMU_PMD_SHIFT_SOFT)
#define SRMMU_PMD_MASK_SOFT (~(SRMMU_PMD_SIZE_SOFT-1))
// #define SRMMU_PMD_ALIGN(addr) (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK)
enum mbus_module srmmu_modtype;
unsigned int hwbug_bitmask;
int vac_cache_size;
......
......@@ -203,9 +203,10 @@ acpi_ds_method_data_init_args (
while ((index < ACPI_METHOD_NUM_ARGS) && (index < max_param_count) && params[index]) {
/*
* A valid parameter.
* Store the argument in the method/walk descriptor
* Store the argument in the method/walk descriptor.
* Do not copy the arg in order to implement call by reference
*/
status = acpi_ds_store_object_to_local (AML_ARG_OP, index, params[index],
status = acpi_ds_method_data_set_value (AML_ARG_OP, index, params[index],
walk_state);
if (ACPI_FAILURE (status)) {
return_ACPI_STATUS (status);
......
......@@ -56,8 +56,8 @@
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
#define DRV_MODULE_VERSION "2.5"
#define DRV_MODULE_RELDATE "December 22, 2003"
#define DRV_MODULE_VERSION "2.6"
#define DRV_MODULE_RELDATE "February 3, 2004"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
......@@ -5904,7 +5904,8 @@ do { p = orig_p + (reg); \
GET_REG32_LOOP(MSGINT_MODE, 0x0c);
GET_REG32_1(DMAC_MODE);
GET_REG32_LOOP(GRC_MODE, 0x4c);
GET_REG32_LOOP(NVRAM_CMD, 0x24);
if (tp->tg3_flags & TG3_FLAG_NVRAM)
GET_REG32_LOOP(NVRAM_CMD, 0x24);
#undef __GET_REG32
#undef GET_REG32_LOOP
......@@ -7190,26 +7191,33 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
test_desc.addr_lo = buf_dma & 0xffffffff;
test_desc.nic_mbuf = 0x00002100;
test_desc.len = size;
/*
* HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
* the *second* time the tg3 driver was getting loaded after an
* initial scan.
*
* Broadcom tells me:
* ...the DMA engine is connected to the GRC block and a DMA
* reset may affect the GRC block in some unpredictable way...
* The behavior of resets to individual blocks has not been tested.
*
* Broadcom noted the GRC reset will also reset all sub-components.
*/
if (to_device) {
test_desc.cqid_sqid = (13 << 8) | 2;
tw32(RDMAC_MODE, RDMAC_MODE_RESET);
tr32(RDMAC_MODE);
udelay(40);
tw32(RDMAC_MODE, RDMAC_MODE_ENABLE);
tr32(RDMAC_MODE);
udelay(40);
} else {
test_desc.cqid_sqid = (16 << 8) | 7;
tw32(WDMAC_MODE, WDMAC_MODE_RESET);
tr32(WDMAC_MODE);
udelay(40);
tw32(WDMAC_MODE, WDMAC_MODE_ENABLE);
tr32(WDMAC_MODE);
udelay(40);
}
test_desc.flags = 0x00000004;
test_desc.flags = 0x00000005;
for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
u32 val;
......@@ -7368,9 +7376,19 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
/* Remove this if it causes problems for some boards. */
tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
}
tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
/* On 5700/5701 chips, we need to set this bit.
* Otherwise the chip will issue cacheline transactions
* to streamable DMA memory with not all the byte
* enables turned on. This is an error on several
* RISC PCI controllers, in particular sparc64.
*
* On 5703/5704 chips, this bit has been reassigned
* a different meaning. In particular, it is used
* on those chips to enable a PCI-X workaround.
*/
tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
}
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
......@@ -7385,28 +7403,38 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
goto out;
while (1) {
u32 *p, i;
u32 *p = buf, i;
p = buf;
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
p[i] = i;
/* Send the buffer to the chip. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
if (ret)
if (ret) {
printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
break;
}
p = buf;
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
/* validate data reached card RAM correctly. */
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
u32 val;
tg3_read_mem(tp, 0x2100 + (i*4), &val);
if (val != p[i]) {
printk( KERN_ERR " tg3_test_dma() Card buffer currupted on write! (%d != %d)\n", val, i);
/* ret = -ENODEV here? */
}
p[i] = 0;
}
/* Now read it back. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
if (ret)
if (ret) {
printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
break;
}
/* Verify it. */
p = buf;
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
if (p[i] == i)
continue;
......@@ -7417,6 +7445,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
break;
} else {
printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
ret = -ENODEV;
goto out;
}
......
......@@ -38,10 +38,12 @@ extern void kmap_init(void) __init;
/*
* Right now we initialize only a single pte table. It can be extended
* easily, subsequent pte tables have to be allocated in one physical
* chunk of RAM.
* chunk of RAM. Currently the simplest way to do this is to align the
* pkmap region on a pagetable boundary (4MB).
*/
#define PKMAP_BASE (SRMMU_NOCACHE_VADDR + (SRMMU_MAX_NOCACHE_PAGES << PAGE_SHIFT))
#define LAST_PKMAP 1024
#define PKMAP_SIZE (LAST_PKMAP << PAGE_SHIFT)
#define PKMAP_BASE SRMMU_PMD_ALIGN_SOFT(SRMMU_NOCACHE_VADDR + (SRMMU_MAX_NOCACHE_PAGES << PAGE_SHIFT))
#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
......
......@@ -36,6 +36,25 @@
#define SRMMU_PMD_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
#define SRMMU_PGD_TABLE_SIZE 0x400 /* 256 entries, 4 bytes a piece */
/*
* To support pagetables in highmem, Linux introduces APIs which
* return struct page* and generally manipulate page tables when
* they are not mapped into kernel space. Our hardware page tables
* are smaller than pages. We lump hardware tabes into big, page sized
* software tables.
*
* PMD_SHIFT determines the size of the area a second-level page table entry
* can map, and our pmd_t is 16 times larger than normal.
*/
#define SRMMU_PTRS_PER_PTE_SOFT (PAGE_SIZE/4) /* 16 hard tables per 4K page */
#define SRMMU_PTRS_PER_PMD_SOFT 4 /* Each pmd_t contains 16 hard PTPs */
#define SRMMU_PTE_SZ_SOFT PAGE_SIZE /* same as above, in bytes */
#define SRMMU_PMD_SHIFT_SOFT 22
#define SRMMU_PMD_SIZE_SOFT (1UL << SRMMU_PMD_SHIFT_SOFT)
#define SRMMU_PMD_MASK_SOFT (~(SRMMU_PMD_SIZE_SOFT-1))
#define SRMMU_PMD_ALIGN_SOFT(addr) (((addr)+SRMMU_PMD_SIZE_SOFT-1)&SRMMU_PMD_MASK_SOFT)
/* Definition of the values in the ET field of PTD's and PTE's */
#define SRMMU_ET_MASK 0x3
#define SRMMU_ET_INVALID 0x0
......
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