Commit 320e1098 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Rob Herring

dt-bindings: PCI: update references to Designware schema

Now that its contents were converted to a DT schema, replace
the references for the old file on existing properties.
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/dfff4d94631546c53450d1baeddc694dd26b5c36.1626608375.git.mchehab+huawei@kernel.orgSigned-off-by: default avatarRob Herring <robh@kernel.org>
parent 0f8b97d8
...@@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller ...@@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller
Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt. Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here: Additional properties are described here:
...@@ -33,7 +33,7 @@ Required properties: ...@@ -33,7 +33,7 @@ Required properties:
- phy-names: must contain "pcie" - phy-names: must contain "pcie"
- device_type: - device_type:
should be "pci". As specified in designware-pcie.txt should be "pci". As specified in snps,dw-pcie.yaml
Example configuration: Example configuration:
......
* Axis ARTPEC-6 PCIe interface * Axis ARTPEC-6 PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt. and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties: Required properties:
- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
......
* Freescale i.MX6 PCIe interface * Freescale i.MX6 PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt. and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties: Required properties:
- compatible: - compatible:
......
...@@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description ...@@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description
The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
It shares common functions with the DesignWare PCIe core driver and inherits It shares common functions with the DesignWare PCIe core driver and inherits
common properties defined in common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt. Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here: Additional properties are described here:
......
...@@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description ...@@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt. Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here: Additional properties are described here:
......
Freescale Layerscape PCIe controller Freescale Layerscape PCIe controller
This PCIe host controller is based on the Synopsys DesignWare PCIe IP This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt. and thus inherits all the common properties defined in snps,dw-pcie.yaml.
This controller derives its clocks from the Reset Configuration Word (RCW) This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset. which is used to describe the PLL settings at the time of chip-reset.
......
NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
This PCIe controller is based on the Synopsis Designware PCIe IP This PCIe controller is based on the Synopsis Designware PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt. and thus inherits all the common properties defined in snps,dw-pcie.yaml and
snps,dw-pcie-ep.yaml.
Some of the controller instances are dual mode where in they can work either Some of the controller instances are dual mode where in they can work either
in root port mode or endpoint mode but one at a time. in root port mode or endpoint mode but one at a time.
...@@ -22,7 +23,7 @@ Required properties: ...@@ -22,7 +23,7 @@ Required properties:
property. property.
- reg-names: Must include the following entries: - reg-names: Must include the following entries:
"appl": Controller's application logic registers "appl": Controller's application logic registers
"config": As per the definition in designware-pcie.txt "config": As per the definition in snps,dw-pcie.yaml
"atu_dma": iATU and DMA registers. This is where the iATU (internal Address "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
Translation Unit) registers of the PCIe core are made available Translation Unit) registers of the PCIe core are made available
for SW access. for SW access.
......
* Marvell Armada 7K/8K PCIe interface * Marvell Armada 7K/8K PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt. and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties: Required properties:
- compatible: "marvell,armada8k-pcie" - compatible: "marvell,armada8k-pcie"
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
PCI core. It inherits common properties defined in PCI core. It inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt. Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Properties of the host controller node that differ from it are: Properties of the host controller node that differ from it are:
......
...@@ -34,22 +34,22 @@ ...@@ -34,22 +34,22 @@
- device_type: - device_type:
Usage: required Usage: required
Value type: <string> Value type: <string>
Definition: Should be "pci". As specified in designware-pcie.txt Definition: Should be "pci". As specified in snps,dw-pcie.yaml
- #address-cells: - #address-cells:
Usage: required Usage: required
Value type: <u32> Value type: <u32>
Definition: Should be 3. As specified in designware-pcie.txt Definition: Should be 3. As specified in snps,dw-pcie.yaml
- #size-cells: - #size-cells:
Usage: required Usage: required
Value type: <u32> Value type: <u32>
Definition: Should be 2. As specified in designware-pcie.txt Definition: Should be 2. As specified in snps,dw-pcie.yaml
- ranges: - ranges:
Usage: required Usage: required
Value type: <prop-encoded-array> Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt Definition: As specified in snps,dw-pcie.yaml
- interrupts: - interrupts:
Usage: required Usage: required
...@@ -64,17 +64,17 @@ ...@@ -64,17 +64,17 @@
- #interrupt-cells: - #interrupt-cells:
Usage: required Usage: required
Value type: <u32> Value type: <u32>
Definition: Should be 1. As specified in designware-pcie.txt Definition: Should be 1. As specified in snps,dw-pcie.yaml
- interrupt-map-mask: - interrupt-map-mask:
Usage: required Usage: required
Value type: <prop-encoded-array> Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt Definition: As specified in snps,dw-pcie.yaml
- interrupt-map: - interrupt-map:
Usage: required Usage: required
Value type: <prop-encoded-array> Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt Definition: As specified in snps,dw-pcie.yaml
- clocks: - clocks:
Usage: required Usage: required
......
...@@ -13,10 +13,10 @@ maintainers: ...@@ -13,10 +13,10 @@ maintainers:
description: |+ description: |+
Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in PCIe IP and thus inherits all the common properties defined in
designware-pcie.txt. snps,dw-pcie.yaml.
allOf: allOf:
- $ref: /schemas/pci/pci-bus.yaml# - $ref: /schemas/pci/snps,dw-pcie.yaml#
properties: properties:
compatible: compatible:
......
...@@ -10,14 +10,14 @@ description: |+ ...@@ -10,14 +10,14 @@ description: |+
SiFive FU740 PCIe host controller is based on the Synopsys DesignWare SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt. Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
maintainers: maintainers:
- Paul Walmsley <paul.walmsley@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com>
- Greentime Hu <greentime.hu@sifive.com> - Greentime Hu <greentime.hu@sifive.com>
allOf: allOf:
- $ref: /schemas/pci/pci-bus.yaml# - $ref: /schemas/pci/snps,dw-pcie.yaml#
properties: properties:
compatible: compatible:
......
...@@ -10,13 +10,13 @@ description: | ...@@ -10,13 +10,13 @@ description: |
UniPhier PCIe endpoint controller is based on the Synopsys DesignWare UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt. Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
maintainers: maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com> - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf: allOf:
- $ref: "pci-ep.yaml#" - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
properties: properties:
compatible: compatible:
......
...@@ -12,7 +12,7 @@ PCIe DesignWare Controller ...@@ -12,7 +12,7 @@ PCIe DesignWare Controller
number of PHYs as specified in *phys* property. number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec. where <X> is the instance number of the pcie from the HW spec.
- num-lanes as specified in ../designware-pcie.txt - num-lanes as specified in ../snps,dw-pcie.yaml
- ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
module and the register offset to specify lane module and the register offset to specify lane
selection. selection.
...@@ -32,7 +32,7 @@ HOST MODE ...@@ -32,7 +32,7 @@ HOST MODE
device_type, device_type,
ranges, ranges,
interrupt-map-mask, interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt interrupt-map : as specified in ../snps,dw-pcie.yaml
- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
should contain the register offset within syscon should contain the register offset within syscon
and the 2nd argument should contain the bit field and the 2nd argument should contain the bit field
......
...@@ -6,7 +6,7 @@ on Socionext UniPhier SoCs. ...@@ -6,7 +6,7 @@ on Socionext UniPhier SoCs.
UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and inherits It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt. Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Required properties: Required properties:
- compatible: Should be "socionext,uniphier-pcie". - compatible: Should be "socionext,uniphier-pcie".
......
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