Commit 328329a7 authored by Anton Vorontsov's avatar Anton Vorontsov Committed by Linus Torvalds

spi_mpc83xx handles other processors with QUICC engine

Currently, all QE SPI controllers are almost the same comparing to
MPC83xx's, thus let's use that driver for them.

Tested to work on MPC85xx in loopback mode.
Signed-off-by: default avatarAnton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent d1e44d9c
...@@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC ...@@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC
Controller in master SPI mode. Controller in master SPI mode.
config SPI_MPC83xx config SPI_MPC83xx
tristate "Freescale MPC83xx SPI controller" tristate "Freescale MPC83xx/QUICC Engine SPI controller"
depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
select SPI_BITBANG select SPI_BITBANG
help help
This enables using the Freescale MPC83xx SPI controller in master This enables using the Freescale MPC83xx and QUICC Engine SPI
mode. controllers in master mode.
Note, this driver uniquely supports the SPI controller on the MPC83xx Note, this driver uniquely supports the SPI controller on the MPC83xx
family of PowerPC processors. The MPC83xx uses a simple set of shift family of PowerPC processors, plus processors with QUICC Engine
registers for data (opposed to the CPM based descriptor model). technology. This driver uses a simple set of shift registers for data
(opposed to the CPM based descriptor model).
config SPI_OMAP_UWIRE config SPI_OMAP_UWIRE
tristate "OMAP1 MicroWire" tristate "OMAP1 MicroWire"
......
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