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Commit 330a5a46 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'imx-fixes-5.4' of... 

Merge tag 'imx-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.4:
 - Re-enable SNVS power key for imx6q-logicpd board which was accidentally
   disabled by a SoC level change.
 - Fix I2C switches on vf610-zii-scu4-aib board by specifying property
   i2c-mux-idle-disconnect.
 - A fix on imx-scu API that reads UID from firmware to avoid kernel NULL
   pointer dump.
 - A series from Anson to correct i.MX7 GPT and i.MX8 USDHC IPG clock.
 - A fix on DRM_MSM Kconfig regression on i.MX5 by adding the option
   explicitly into imx_v6_v7_defconfig.
 - Fix ARM regulator states issue for zii-ultra board, which is impacting
   stability of the board.
 - A correction on CPU core idle state name for LayerScape LX2160A SoC.

* tag 'imx-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx_v6_v7_defconfig: Enable CONFIG_DRM_MSM
  arm64: dts: imx8mn: Use correct clock for usdhc's ipg clk
  arm64: dts: imx8mm: Use correct clock for usdhc's ipg clk
  arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk
  ARM: dts: imx7s: Correct GPT's ipg clock source
  ARM: dts: vf610-zii-scu4-aib: Specify 'i2c-mux-idle-disconnect'
  ARM: dts: imx6q-logicpd: Re-Enable SNVS power key
  arm64: dts: lx2160a: Correct CPU core idle state name
  arm64: dts: zii-ultra: fix ARM regulator states
  soc: imx: imx-scu: Getting UID from SCU should have response

Link: https://lore.kernel.org/r/20191017141851.GA22506@dragonSigned-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 279296ed 95993238
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arch/arm/boot/dts/imx6-logicpd-som.dtsi
View file @ 330a5a46
...@@ -207,6 +207,10 @@ &reg_soc ...@@ -207,6 +207,10 @@ &reg_soc
vin-supply = <&sw1c_reg>; vin-supply = <&sw1c_reg>;
}; };
&snvs_poweroff {
status = "okay";
};
&iomuxc { &iomuxc {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_hog>;
......
arch/arm/boot/dts/imx7s.dtsi
View file @ 330a5a46
...@@ -448,7 +448,7 @@ gpt1: gpt@302d0000 { ...@@ -448,7 +448,7 @@ gpt1: gpt@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d0000 0x10000>; reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
<&clks IMX7D_GPT1_ROOT_CLK>; <&clks IMX7D_GPT1_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
}; };
...@@ -457,7 +457,7 @@ gpt2: gpt@302e0000 { ...@@ -457,7 +457,7 @@ gpt2: gpt@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302e0000 0x10000>; reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
<&clks IMX7D_GPT2_ROOT_CLK>; <&clks IMX7D_GPT2_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
status = "disabled"; status = "disabled";
...@@ -467,7 +467,7 @@ gpt3: gpt@302f0000 { ...@@ -467,7 +467,7 @@ gpt3: gpt@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302f0000 0x10000>; reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
<&clks IMX7D_GPT3_ROOT_CLK>; <&clks IMX7D_GPT3_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
status = "disabled"; status = "disabled";
...@@ -477,7 +477,7 @@ gpt4: gpt@30300000 { ...@@ -477,7 +477,7 @@ gpt4: gpt@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x30300000 0x10000>; reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
<&clks IMX7D_GPT4_ROOT_CLK>; <&clks IMX7D_GPT4_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
status = "disabled"; status = "disabled";
......
arch/arm/boot/dts/vf610-zii-scu4-aib.dts
View file @ 330a5a46
...@@ -602,6 +602,7 @@ tca9548@70 { ...@@ -602,6 +602,7 @@ tca9548@70 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x70>; reg = <0x70>;
i2c-mux-idle-disconnect;
sff0_i2c: i2c@1 { sff0_i2c: i2c@1 {
#address-cells = <1>; #address-cells = <1>;
...@@ -640,6 +641,7 @@ tca9548@71 { ...@@ -640,6 +641,7 @@ tca9548@71 {
reg = <0x71>; reg = <0x71>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
i2c-mux-idle-disconnect;
sff5_i2c: i2c@1 { sff5_i2c: i2c@1 {
#address-cells = <1>; #address-cells = <1>;
......
arch/arm/configs/imx_v6_v7_defconfig
View file @ 330a5a46
...@@ -276,6 +276,7 @@ CONFIG_VIDEO_OV5640=m ...@@ -276,6 +276,7 @@ CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m CONFIG_VIDEO_OV5645=m
CONFIG_IMX_IPUV3_CORE=y CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y CONFIG_DRM=y
CONFIG_DRM_MSM=y
CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
......
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View file @ 330a5a46
...@@ -33,7 +33,7 @@ cpu@0 { ...@@ -33,7 +33,7 @@ cpu@0 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@1 { cpu@1 {
...@@ -49,7 +49,7 @@ cpu@1 { ...@@ -49,7 +49,7 @@ cpu@1 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@100 { cpu@100 {
...@@ -65,7 +65,7 @@ cpu@100 { ...@@ -65,7 +65,7 @@ cpu@100 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@101 { cpu@101 {
...@@ -81,7 +81,7 @@ cpu@101 { ...@@ -81,7 +81,7 @@ cpu@101 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@200 { cpu@200 {
...@@ -97,7 +97,7 @@ cpu@200 { ...@@ -97,7 +97,7 @@ cpu@200 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@201 { cpu@201 {
...@@ -113,7 +113,7 @@ cpu@201 { ...@@ -113,7 +113,7 @@ cpu@201 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@300 { cpu@300 {
...@@ -129,7 +129,7 @@ cpu@300 { ...@@ -129,7 +129,7 @@ cpu@300 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@301 { cpu@301 {
...@@ -145,7 +145,7 @@ cpu@301 { ...@@ -145,7 +145,7 @@ cpu@301 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@400 { cpu@400 {
...@@ -161,7 +161,7 @@ cpu@400 { ...@@ -161,7 +161,7 @@ cpu@400 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>; next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@401 { cpu@401 {
...@@ -177,7 +177,7 @@ cpu@401 { ...@@ -177,7 +177,7 @@ cpu@401 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>; next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@500 { cpu@500 {
...@@ -193,7 +193,7 @@ cpu@500 { ...@@ -193,7 +193,7 @@ cpu@500 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>; next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@501 { cpu@501 {
...@@ -209,7 +209,7 @@ cpu@501 { ...@@ -209,7 +209,7 @@ cpu@501 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>; next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@600 { cpu@600 {
...@@ -225,7 +225,7 @@ cpu@600 { ...@@ -225,7 +225,7 @@ cpu@600 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>; next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@601 { cpu@601 {
...@@ -241,7 +241,7 @@ cpu@601 { ...@@ -241,7 +241,7 @@ cpu@601 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>; next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@700 { cpu@700 {
...@@ -257,7 +257,7 @@ cpu@700 { ...@@ -257,7 +257,7 @@ cpu@700 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>; next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@701 { cpu@701 {
...@@ -273,7 +273,7 @@ cpu@701 { ...@@ -273,7 +273,7 @@ cpu@701 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>; next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cluster0_l2: l2-cache0 { cluster0_l2: l2-cache0 {
...@@ -340,9 +340,9 @@ cluster7_l2: l2-cache7 { ...@@ -340,9 +340,9 @@ cluster7_l2: l2-cache7 {
cache-level = <2>; cache-level = <2>;
}; };
cpu_pw20: cpu-pw20 { cpu_pw15: cpu-pw15 {
compatible = "arm,idle-state"; compatible = "arm,idle-state";
idle-state-name = "PW20"; idle-state-name = "PW15";
arm,psci-suspend-param = <0x0>; arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>; entry-latency-us = <2000>;
exit-latency-us = <2000>; exit-latency-us = <2000>;
......
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View file @ 330a5a46
...@@ -694,7 +694,7 @@ usdhc1: mmc@30b40000 { ...@@ -694,7 +694,7 @@ usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>; reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>, clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC1_ROOT>; <&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
...@@ -710,7 +710,7 @@ usdhc2: mmc@30b50000 { ...@@ -710,7 +710,7 @@ usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>; reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>, clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC2_ROOT>; <&clk IMX8MM_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
...@@ -724,7 +724,7 @@ usdhc3: mmc@30b60000 { ...@@ -724,7 +724,7 @@ usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>; reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>, clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC3_ROOT>; <&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
......
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View file @ 330a5a46
...@@ -569,7 +569,7 @@ usdhc1: mmc@30b40000 { ...@@ -569,7 +569,7 @@ usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>; reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>, clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC1_ROOT>; <&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
...@@ -585,7 +585,7 @@ usdhc2: mmc@30b50000 { ...@@ -585,7 +585,7 @@ usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>; reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>, clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC2_ROOT>; <&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
...@@ -599,7 +599,7 @@ usdhc3: mmc@30b60000 { ...@@ -599,7 +599,7 @@ usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>; reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>, clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC3_ROOT>; <&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
......
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View file @ 330a5a46
...@@ -89,8 +89,8 @@ reg_arm: regulator-arm { ...@@ -89,8 +89,8 @@ reg_arm: regulator-arm {
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>; regulator-max-microvolt = <1000000>;
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
states = <1000000 0x0 states = <1000000 0x1
900000 0x1>; 900000 0x0>;
regulator-always-on; regulator-always-on;
}; };
}; };
......
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View file @ 330a5a46
...@@ -850,7 +850,7 @@ usdhc1: mmc@30b40000 { ...@@ -850,7 +850,7 @@ usdhc1: mmc@30b40000 {
"fsl,imx7d-usdhc"; "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>; reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>, clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>; <&clk IMX8MQ_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
...@@ -867,7 +867,7 @@ usdhc2: mmc@30b50000 { ...@@ -867,7 +867,7 @@ usdhc2: mmc@30b50000 {
"fsl,imx7d-usdhc"; "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>; reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>, clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC2_ROOT>; <&clk IMX8MQ_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
......
drivers/soc/imx/soc-imx-scu.c
View file @ 330a5a46
...@@ -46,7 +46,7 @@ static ssize_t soc_uid_show(struct device *dev, ...@@ -46,7 +46,7 @@ static ssize_t soc_uid_show(struct device *dev,
hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID; hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID;
hdr->size = 1; hdr->size = 1;
ret = imx_scu_call_rpc(soc_ipc_handle, &msg, false); ret = imx_scu_call_rpc(soc_ipc_handle, &msg, true);
if (ret) { if (ret) {
pr_err("%s: get soc uid failed, ret %d\n", __func__, ret); pr_err("%s: get soc uid failed, ret %d\n", __func__, ret);
return ret; return ret;
......
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