arm64: dts: mediatek: Format mediatek,larbs as an array of phandles

Commit 39bd2b6a ("dt-bindings: Improve phandle-array schemas")
updated the mediatek,larbs property in the mediatek,iommu.yaml
dt-binding to make it clearer that the phandles passed to the property
are independent, rather than subsequent arguments to the first phandle.

Update the mediatek,larbs property in the arm64 Devicetrees to use the
same formatting. This change doesn't impact any behavior: the compiled
dtb is exactly the same. It does however fix the warnings generated by
dtbs_check.
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220301203147.1143782-2-nfraprado@collabora.comSigned-off-by: Matthias Brugger <matthias.bgg@gmail.com>

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

@@ -329,8 +329,8 @@ iommu0: iommu@10205000 {
 		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&infracfg CLK_INFRA_M4U>;
 		clock-names = "bclk";
-		mediatek,larbs = <&larb0 &larb1 &larb2
-				  &larb3 &larb6>;
+		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+				 <&larb3>, <&larb6>;
 		#iommu-cells = <1>;
 	};
 
@@ -346,7 +346,7 @@ iommu1: iommu@1020a000 {
 		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&infracfg CLK_INFRA_M4U>;
 		clock-names = "bclk";
-		mediatek,larbs = <&larb4 &larb5 &larb7>;
+		mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
 		#iommu-cells = <1>;
 	};
 

arch/arm64/boot/dts/mediatek/mt8167.dtsi

@@ -174,7 +174,7 @@ larb2: larb@16010000 {
 		iommu: m4u@10203000 {
 			compatible = "mediatek,mt8167-m4u";
 			reg = <0 0x10203000 0 0x1000>;
-			mediatek,larbs = <&larb0 &larb1 &larb2>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
 			#iommu-cells = <1>;
 		};

arch/arm64/boot/dts/mediatek/mt8173.dtsi

@@ -588,8 +588,8 @@ iommu: iommu@10205000 {
 			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&infracfg CLK_INFRA_M4U>;
 			clock-names = "bclk";
-			mediatek,larbs = <&larb0 &larb1 &larb2
-					  &larb3 &larb4 &larb5>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+					 <&larb3>, <&larb4>, <&larb5>;
 			#iommu-cells = <1>;
 		};
 

arch/arm64/boot/dts/mediatek/mt8183.dtsi

@@ -682,8 +682,8 @@ iommu: iommu@10205000 {
 			compatible = "mediatek,mt8183-m4u";
 			reg = <0 0x10205000 0 0x1000>;
 			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
-			mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
-					  &larb4 &larb5 &larb6>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
+					 <&larb4>, <&larb5>, <&larb6>;
 			#iommu-cells = <1>;
 		};