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Commit 34542ff5 authored by Gabor Juhos's avatar Gabor Juhos Committed by John W. Linville
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rt2x00: rt2800lib: add TX power configuration for RT3593 

Based on the Ralink DPO_RT5572_LinuxSTA_2.6.0.1_20120629
driver.

References:
  RTMPReadTxPwrPerRateExt in chips/rt3593.c
  RT3593_AsicGetTxPowerOffset in chips/rt3593.c
Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Acked-by: default avatarStanislaw Gruszka <stf_xl@wp.pl>
Acked-by: default avatarGertjan van Wingerde <gwingerde@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent d63f7e8c
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Showing with 538 additions and 3 deletions
drivers/net/wireless/rt2x00/rt2800.h
View file @ 34542ff5
......@@ -1083,6 +1083,15 @@
#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
/* bits for 3T devices */
#define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
/*
* TX_PWR_CFG_1:
......@@ -1096,6 +1105,15 @@
#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
/* bits for 3T devices */
#define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
/*
* TX_PWR_CFG_2:
......@@ -1109,6 +1127,15 @@
#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
/* bits for 3T devices */
#define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
/*
* TX_PWR_CFG_3:
......@@ -1122,6 +1149,15 @@
#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
/* bits for 3T devices */
#define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
/*
* TX_PWR_CFG_4:
......@@ -1131,6 +1167,11 @@
#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
/* bits for 3T devices */
#define TX_PWR_CFG_3_STBC4_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_3_STBC4_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_3_STBC6_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_3_STBC6_CH1 FIELD32(0x0000f000)
/*
* TX_PIN_CFG:
......@@ -1452,6 +1493,81 @@
*/
#define EXP_ACK_TIME 0x1380
/* TX_PWR_CFG_5 */
#define TX_PWR_CFG_5 0x1384
#define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_6 */
#define TX_PWR_CFG_6 0x1388
#define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_0_EXT */
#define TX_PWR_CFG_0_EXT 0x1390
#define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
#define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_1_EXT */
#define TX_PWR_CFG_1_EXT 0x1394
#define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
#define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_2_EXT */
#define TX_PWR_CFG_2_EXT 0x1398
#define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
#define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_3_EXT */
#define TX_PWR_CFG_3_EXT 0x139c
#define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
#define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_4_EXT */
#define TX_PWR_CFG_4_EXT 0x13a0
#define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
/* TX_PWR_CFG_7 */
#define TX_PWR_CFG_7 0x13d4
#define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_8 */
#define TX_PWR_CFG_8 0x13d8
#define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
/* TX_PWR_CFG_9 */
#define TX_PWR_CFG_9 0x13dc
#define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
/*
* RX_FILTER_CFG: RX configuration register.
*/
......
drivers/net/wireless/rt2x00/rt2800lib.c
View file @ 34542ff5
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